ZVP1320A Ver la hoja de datos (PDF) - Diodes Incorporated.

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ZVP1320A

P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

Diodes Incorporated. 

P-CHANNEL ENHANCEMENT

MODE VERTICAL DMOS FET

ISSUE 2 – MARCH 94

FEATURES

* 200 Volt VDS

* RDS(on)=80Ω

ZVP1320A

ABSOLUTE MAXIMUM RATINGS.

PARAMETER

Drain-Source Voltage

Continuous Drain Current at Tamb=25°C

Pulsed Drain Current

Gate Source Voltage

Power Dissipation at Tamb=25°C

Operating and Storage Temperature Range

SYMBOL

VDS

ID

IDM

VGS

Ptot

Tj:Tstg

D

G

S

E-Line

TO92 Compatible

VALUE

-200

-70

-400

± 20

625

-55 to +150

UNIT

V

mA

mA

V

mW

°C

ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).

PARAMETER

SYMBOL MIN. MAX. UNIT CONDITIONS.

Drain-Source Breakdown

Voltage

BVDSS -200

V

ID=-1mA, VGS=0V

Gate-Source Threshold

Voltage

VGS(th) -1.5 -3.5 V

ID=-1mA, VDS= VGS

Gate-Body Leakage

IGSS

Zero Gate Voltage Drain

IDSS

Current

20 nA VGS=± 20V, VDS=0V

-10 µA VDS=-200 V, VGS=0

-50 µA VDS=-160 V, VGS=0V,

T=125°C(2)

On-State Drain Current(1)

ID(on)

Static Drain-Source On-State RDS(on)

Resistance (1)

-100

80

mA VDS=-25 V, VGS=-10V

Ω

VGS=-10V,ID=-50mA

Forward Transconductance gfs

25

(1)(2)

mS VDS=-25V,ID=-50mA

Input Capacitance (2)

Ciss

Common Source Output

Coss

Capacitance (2)

50 pF

15 pF VDS=-25 V, VGS=0V, f=1MHz

Reverse Transfer

Crss

5

pF

Capacitance (2)

Turn-On Delay Time (2)(3)

Rise Time (2)(3)

Turn-Off Delay Time (2)(3)

Fall Time (2)(3)

td(on)

tr

td(off)

tf

8

ns

8

ns

VDD≈-25V, ID=-50mA

8

ns

16 ns

(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2%

(2) Sample test.

3-414

(

3

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