RD28F1602C3B110_03 Ver la hoja de datos (PDF) - Intel

Número de pieza

componentes Descripción

Fabricante

RD28F1602C3B110_03

3 Volt Intel® Advanced+ Boot Block Flash Memory(C3) Stacked-Chip Scale Package Family

Intel 

3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family

Table 8. Block Locking State Transitions

Current State

WP# DQ1 DQ0

Name

Erase/

Program

Allowed?

Next State after Command Input

Lock

Unlock

Lock-Down

0

0

0

Unlocked

Yes

Go To [001]

–

Go To [011]

1

0

0

Unlocked

Yes

Go To [101]

–

Go To [111]

0

0

1 Locked (Default)

No

–

Go To [000]

Go To [011]

1

0

1

Locked

No

–

Go To [100]

Go To [111]

0

1

1

Locked-Down

No

–

–

–

1

1

0

Lock-Down

Yes

1

1

1

Disabled

No

Go To [111]

-

–

Go To [110]

Go To [111]

–

NOTES:

1. “–” indicates no change in the current state.

2. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ1, and Z = DQ0. The current

locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ0, DQ1). DQ0 indicates if a

block is locked (1) or unlocked (0). DQ1 indicates if a block has been locked-down (1) or not (0).

3. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). holding WP# = 0 is the recommended

default.

4. The “Erase/Program Allowed?” column shows whether erase and program operations are enabled (Yes) or disabled (No) in

that block’s current locking state.

5. The “Lock Command Input Result [Next State]” column shows the result of writing the three locking commands (Lock, Unlock,

Lock-Down) in the current locking state. For example, “Goes To [001]” would mean that writing the command to a block in the

current locking state would change it to [001].

6. The 128 bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel

factory with a unique 64 bit number, which is unchangeable. The other segment is left blank for customer designs to program

as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming.

3.8

3.8.1

3.8.2

128 Bit Protection Register

The 3 Volt Intel® Advanced+ Stacked-CSP architecture includes a 128-bit protection register than

can be used to increase the security of a system design. For example, the number contained in the

protection register can be used to “mate” the flash component with other system components such

as the CPU or ASIC, preventing device substitution.

Reading the Protection Register

The protection register is read in the configuration read mode. The device is switched to this mode

by writing the Read Configuration command (90h). Once in this mode, read cycles from addresses

shown in Appendix E retrieve the specified information. To return to read array mode, write the

Read Array command (FFh).

Programming the Protection Register (C0h)

The protection register bits are programmed using the two-cycle Protection Program command.

The 64-bit number is programmed 16 bits at a time for word-wide parts. First write the Protection

Program Setup command, C0h. The next write to the device will latch in address and data and

program the specified location. The allowable addresses are shown in Appendix E. See Figure 20,

“Protection Register Programming Flowchart” on page 51.

Datasheet

21

Share Link: