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MC145406P

Driver/Receiver EIA 232-E and CCITT V.28 (Formerly RS-232-D)

Motorola => Freescale 

APPLICATIONS INFORMATION

The MC145406 has been designed to meet the electrical

specifications of standards EIA 232–E and CCITT V.28.

EIA 232–E defines the electrical and physical interface be-

tween Data Communication Equipment (DCE) and Data

Terminal Equipment (DTE). A DCE is connected to a DTE

using a cable that typically carries up to 25 leads. These

leads, referred to as interchange circuits, allow the transfer

of timing, data, control, and test signals. Electrically this

transfer requires level shifting between the TTL/CMOS log-

ic levels of the computer or modem and the high voltage lev-

els of EIA 232–E, which can range from ± 3 to ± 25 V. The

MC145406 provides the necessary level shifting as well as

meeting other aspects of the EIA 232–E specification.

DRIVERS

As defined by the specification, an EIA 232–E driver pres-

ents a voltage of between ± 5 to ± 15 V into a load of be-

tween 3 to 7 kΩ. A logic 1 at the driver input results in a

voltage of between – 5 to – 15 V. A logic 0 results in a voltage

between + 5 to + 15V. When operating VDD and VSS at ± 7 to

± 12 V, the MC145406 meets this requirement. When operat-

ing at ± 5 V, the MC145406 drivers produce less than

± 5 V at the output (when terminated), which does not meet

EIA 232–E specification. However, the output voltages when

using a ± 5 V power supply are high enough (around

± 4 V) to permit proper reception by an EIA 232–E receiver,

and can be used in applications where strict compliance to

EIA 232–E is not required.

Another requirement of the MC145406 drivers is that

they withstand a short to another driver in the EIA 232–E

cable. The worst–case condition that is permitted by

EIA 232–E is a ± 15 V source that is current limited to 500

mA. The MC145406 drivers can withstand this condition

momentarily. In most short circuit conditions the source

driver will have a series 300 Ω output impedance needed

to satisfy the EIA 232–E driver requirements. This will re-

duce the short circuit current to under 40 mA which is an

acceptable level for the MC145406 to withstand.

Unlike some other drivers, the MC145406 drivers feature

an internally–limited output slew–rate that does not exceed

30 V per µs.

RECEIVERS

The job of an EIA 232–E receiver is to level–shift voltages

in the range of – 25 to + 25 V down to TTL/CMOS logic lev-

els (0 to + 5 V). A voltage of between – 3 and – 25 V on Rx1

is defined as a mark and produces a logic 1 at DO1. A volt-

age between + 3 and + 25 V is a space and produces a logic

zero. While receiving these signals, the Rx inputs must pres-

ent a resistance between 3 and 7 kΩ. Nominally, the input re-

sistance of the Rx1–Rx3 inputs is 5.4 kΩ.

The input threshold of the Rx1–Rx3 inputs is typically

biased at 1.8 V above ground (GND) with typically 800 mV of

hysteresis included to improve noise immunity. The 1.8 V

bias forces the appropriate DO pin to a logic 1 when its Rx

input is open or grounded as called for in the EIA 232–E

specification. Notice that TTL logic levels can be applied to

the Rx inputs in lieu of normal EIA 232–E signal levels. This

might be helpful in situations where access to the modem or

computer through the EIA 232–E connector is necessary

with TTL devices. However, it is important not to connect the

EIA 232–E outputs (Tx1–Tx3) to TTL inputs since TTL oper-

ates off + 5 V only, and may be damaged by the high output

voltage of the MC145406.

The DO outputs are to be connected to a TTL or CMOS

input (such as an input to a modem chip). These outputs

will swing from VCC to ground, allowing the designer to op-

erate the DO and DI pins from digital power supply. The Tx

and Rx sections are independently powered by VDD and

VSS so that one may run logic at + 5 V and the EIA 232–E

signals at ± 12 V.

POWER SUPPLY CONSIDERATIONS

Figure 4 shows a technique to guard against excessive

device current.

The diode D1 prevents excessive current from flowing

through an internal diode from the VCC pin to the VDD pin

when VDD < VCC by approximately 0.6 V. This high current

condition can exist for a short period of time during power

up/down. Additionally, if the + 12 V supply is switched off

while the + 5 V is on and the off supply is a low impedance

to ground, the diode D1 will prevent current flow through

the internal diode.

The diode D2 is used as a voltage clamp, to prevent VSS

from drifting positive to VCC, in the event that power is re-

moved from VSS (Pin 12). If VSS power is removed, and the

impedance from the VSS pin to ground is greater than

approximately 3 kΩ, this pin will be pulled to VCC by internal

circuitry causing excessive current in the VCC pin.

If by design, neither of the above conditions are allowed

to exist, then the diodes D1 and D2 are not required.

ESD PROTECTION

ESD protection on IC devices that have their pins accessi-

ble to the outside world is essential. High static voltages ap-

plied to the pins when someone touches them either directly

or indirectly can cause damage to gate oxides and transistor

junctions by coupling a portion of the energy from the I/O pin

to the power supply buses of the IC. This coupling will usually

occur through the internal ESD protection diodes. The key to

protecting the IC is to shunt as much of the energy to ground

as possible before it enters the IC. Figure 4 shows a tech-

nique which will clamp the ESD voltage at approximately ±

15 V using the MMVZ15VDLT1. Any residual voltage which

appears on the supply pins is shunted to ground through the

capacitors C1–C3. This scheme has provided protection to

the interface part up to ± 10 kV, using the human body model

test.

MOTOROLA

MC145406

5

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