BA7657S Ver la hoja de datos (PDF) - ROHM Semiconductor
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BA7657S Datasheet PDF : 17 Pages
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●Description of operations
BH7659FS
1) Analog SW block
R, G, and B chroma signals are switched in two channels.
INA is selected by applying a high-level voltage to the CTL pin, and INB is selected by applying a low-level voltage.
When the power save pin (pin 8) is set to high level, the current to the SW block's output transistors is reduced to lower
the circuit current.
Even during low power mode, signal switching can be performed normally as long as there is no drop in frequency
characteristics.
2) CMOS analog SW block
SDA and SDC signals are switched via an I2C bus to handle two channels of HD and VD synchronization signals, and to
exchange information bidirectionally between a computer and a monitor.
The switching circuits used by this IC handle are configured as CMOS analog switches in order to handle I2C BUS
signals and to transmit input and output signals bidirectionally. (ON resistance: Ron 200 Ω typ.)
●Application circuit
BH7659FS
Input A
R
G
B
VD
SDA
R4
5. 1
R4
5. 1
SCA
HD
R4
5. 1
R4
5. 1
Input B
R
G
B
VD
R4
SDA
R4
SCA
R4
HD
R4
5. 1
5. 1
5. 1
5. 1
C1
VCC
R2
C2
R1
C1
VCC
R2
C2
R1
C1
VCC
R2
C2
R1
C1
VCC
R2
C2
R1
R4
PS:H
C3
C1
VCC
VCC R1 C2
R2
C1
C2
C1
VCC
R2
C2
R1
CTL
IN A: H
IN B: L
R4
C3
R3
1
A
2
B
3
A
4
B
5
A
6
B
7
8
POWER
SAVE
9
10
11
12 N. C.
13
CTL
A
14
R3
B
15
VD OUT
R3
16
R
G
B
A
B
A
VCC
32
C1
31
Ro
30
C2
R OUT
VCC
C1
29
Ro
28
C2
G OUT
VCC
C1
27
Ro
C2
B OUT
26
R3
HD OUT
25
R3
24
R3
23
R3
SCL IO
22
R3
N. C. 21
B
20
R3
A
19
R3
B
18
R3
SDA IO
17
R3
Fig.9
13/16
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