5L35021 Ver la hoja de datos (PDF) - Integrated Device Technology
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5L35021 Datasheet PDF : 37 Pages
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5L35021 Datasheet
Device Features and Functions
Performance Power Balancing
VersaClock 3S features Performance Power Balancing with three individual programmable PLL designs and provides a balance between
performance and power consumption.
The device can operate within single-digit mA low-power operation or support high-performance requirements such as PCIe Gen 3 with
additional power.
In order to satisfy system trade-off, outputs have the option to route from different PLL/input sources.
Table 15. Power Saving Modes Summary
Power Mode
Power-down Mode
Ultra-power-down
External Condition
VDD all connected.
VDD all connected.
Suspend Mode
Only VBAT connected.
Internal Operating Condition
All off, I2C still active.
All off.
All off, only DCO on with RTC
(32.768kHz) output only.
Core Current Consumption
2mA
50μA
2μA
Table 16. Output Source
Source
Xtal REF
32.768kHz
PLL1
PLL2
PLL3
SE1
Xtal REF
32.768kHz
PLL2
PLL3
Outputs
DIFF1
Xtal REF
PLL1
PLL2
PLL3
DIFF2
Xtal REF
PLL1
PLL2
PLL3
Table 17. SE1 Output
SE1
From 32kHz
From PLL3 + Divider 5
From PLL2 + Divider 4
From REF + Divider 4
B36<4>
0
1
1
1
B36<3>
1
0
1
1
B31<1>
0
0
1
0
B29<3>
0
0
0
1
Table 18. DIFF1 Output
DIFF1
From PLL1 + Divider 1
From PLL2 + Divider 3
From REF + Divider 1
B34<7>
0
1
0
B0<3>
0
0
1
©2017 Integrated Device Technology, Inc.
12
July 13, 2017
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