SSM2275 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

SSM2275

Rail-to-Rail Output Audio Amplifiers

Analog Devices 

SSM2275/SSM2475

SPICE Macro-model

The SPICE macro-model for the SSM2275 is shown in Listing

1 on the following page. This model is based on typical values

for the device and can be downloaded from Analog Devices’

Internet site at www.analog.com. The model uses a common

emitter output stage to provide rail-to-rail performance. A resis-

tor and dc voltage source, in series with the collector, accurately

portray output dropout voltage versus output current. The

VCMH and VCML sources set the upper and lower limits of

the input common mode voltage range. Both are set up as a

function of the supply voltage to mimic the varying common

mode range with supply voltage. The EOS voltage source estab-

lishes the offset voltage and is also used to create the common-

mode rejection and power supply rejection characteristics for

the model.

A secondary pole section is also set up to vary the gain band-

width product and phase margin of the model based on the

supply voltage. The H1 and VR1 sources set up an equivalent

resistor that is linearly varied with supply voltage. This equiva-

lent resistance, in parallel with C2, creates the secondary pole.

G2 is also linearly varied to increase the GBW at higher supply

voltages. With a supply voltage of 5 V, the gain bandwidth

product is 6.3 MHz with a 47 degree phase margin. At a 30 V

supply voltage, the GBW product moves out to 7.5 MHz with

48° phase margin.

The broadband input referred voltage noise for the model is

6.8 nV/√Hz. Flicker noise characteristics are also accurately

modeled with the 1/f corner frequency set through the KF and

AF terms in the input stage transistors. Finally, a voltage-con-

trolled current source, GSY, is used to model the amplifier’s

supply current versus supply voltage characteristics.

+5V SUPPLY

1 VL

LL

2

DL

3

CK

4

DR

5

LR

6

18-BIT

DAC

18-BIT

SERIAL

REG.

VREF

18-BIT

SERIAL

REG.

AD1868

VREF

7 DGND

VBR 18-BIT

8

DAC

VBL

16

15

VOL 14

13

AGND 12

11

VOR

10

VS 9

7.68k⍀

330pF

7.68k⍀

330pF

1/2

SSM2275

3

9.76k⍀

2

8

1

4

220␮F

47kΩ

LEFT

CHANNEL

OUTPUT

7.68k⍀

100pF

7.68k⍀

9.76k⍀

100pF

6

1/2

SSM2275 7

5

220␮F

47k⍀

RIGHT

CHANNEL

OUTPUT

Figure 42. A Smoothing Filter for an 18-Bit Stereo DAC

–14–

REV. A

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