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ATTL7554BP

L7554 Low-Power SLIC

Agere -> LSI Corporation 

L7554 Low-Power SLIC

Data Sheet

March 1997

Applications (continued)

ac Design (continued)

Example 1, Real Termination

The following design equations refer to the circuit in

Figure 32. Use these to synthesize real termination

impedance.

Termination Impedance:

zt = -v---T---⁄--R-

–itr

zt = 2RP + 80 Ω + -------------3--2---0---0--------------

1 + -R----T--1- + --R----T---1--

RGP RRCV

Receive Gain:

grcv = v----T---⁄--R-

vfr

grcv = ---------------------------------8---------------------------------

1

+

-R---R---C---V-

RT1

+

R--R--R--G-C--P-V-

1

+

Z----Tz---t⁄--R-

Transmit Gain:

gtx = v-v---Tg--s-⁄-x-R-

gtx = --R---X-- × --4--0---0---

RT2 ZT ⁄ R

Hybrid Balance:

hbal = 20log -V-V---g--f-s-r--x-

To optimize the hybrid balance, the sum of the currents

at the VFX input of the codec op amp should be set to

0. The following expressions assume that the test net-

work is the same as the termination impedance.

hbal = 20log R--R--H--X-B- – gtx × grcv

Example 2, Complex Termination:

For complex termination, the spare op amp is used

(see Figure 33).

zt

=

2

R

P

+

80

Ω

+

-------------3--2---0---0--------------(

1 + -R----T--3- + --R----T---3--

R-Z----TT---54-

)

RGN RRCV

= 2RP + 80 Ω + k(ZT5)

grcv = -------------------------------------8--------------------------------------

RHB1=+g----R--t-R--x--R----RT--×-C---3--X-V--g---+r-c--v--R-R---R--G--C-N--V-1 + Z----zT---t/-R--

gtx = –-R---R--T---6X- × -Z4---0T---/0-R-- × R-Z----TT---54-

The hybrid balance equation is the same as in

Example 1.

PCB Layout Information

Make the leads to BGND and VBAT as wide as possible

for thermal and electrical reasons. Also, maximize the

amount of PCB copper in the area of—and specifically

on—the leads connected to this device for the lowest

operating temperature.

When powering the device, ensure that no external

potential creates a voltage on any pin of the device that

exceeds the device ratings. In this application, some of

the conditions that cause such potentials during pow-

erup are the following: 1) an inductor connected to PT

and PR (this can force an overvoltage on VBAT through

the protection devices if the VBAT connection chatters)

and 2) inductance in the VBAT lead (this could resonate

with the VBAT filter capacitor to cause a destructive

overvoltage).

This device is normally used on a circuit card that is

subjected to hot plug-in, meaning the card is plugged

into a biased backplane connector. In order to prevent

damage to the IC, all ground connections must be

applied before, and removed after, all other connec-

tions.

26

Lucent Technologies Inc.

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