ISP1583 Ver la hoja de datos (PDF) - NXP Semiconductors.
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ISP1583 Datasheet PDF : 100 Pages
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NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
8.13.2 Interrupt control
Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The behavior
of this bit is given in Figure 6.
The following illustrations are only applicable for level trigger.
Event A: When an interrupt event occurs (for example, SOF interrupt) with bit GLINTENA
set to logic 0, an interrupt will not be generated at pin INT. It will, however, be registered in
the corresponding Interrupt register bit.
Event B: When bit GLINTENA is set to logic 1, pin INT is asserted because bit SOF in the
Interrupt register is already set.
Event C: If the firmware sets bit GLINTENA to logic 0, pin INT will still be asserted. The
bold line shows the desired behavior of pin INT.
Deassertion of pin INT can be achieved either by clearing all the bits in the Interrupt
register or the DMA Interrupt Reason register, depending on the event.
Remark: When clearing an interrupt event, perform write to all the bytes of the register.
For more information on interrupt control, see Section 9.2.2, Section 9.2.5 and
Section 9.5.1.
A
B
C
INT pin
GLINTENA = 0
(during this time,
an interrupt event
occurs, for example,
SOF asserted)
GLINTENA = 1
SOF asserted
GLINTENA = 0
SOF asserted
004aaa394
Pin INT: HIGH = deassert; LOW = assert (individual interrupts are enabled).
Fig 6. Behavior of bit GLINTENA
8.14 VBUS sensing
The VBUS pin is one of the ways to wake up the clock when the ISP1583 is suspended
with bit CLKAON set to logic 0 (clock off option).
To detect whether the host is connected or not, that is VBUS sensing, a 1 MΩ resistor and
a 1 µF electrolytic or tantalum capacitor must be added to damp the overshoot on plug in.
ISP1583_7
Product data sheet
Rev. 07 — 22 September 2008
© NXP B.V. 2008. All rights reserved.
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