Philips Semiconductors
Low power dual-band GSM transceiver
with an image rejecting front-end
Objective specification
UAA3522HL
SERIAL TIMING CHARACTERISTICS
General conditions: VCC = 2.8 V; Tamb = 25 °C; see Fig.6; unless otherwise specified.
SYMBOL
PARAMETER
MIN. TYP. MAX. UNIT
Serial programming clock (pin CLK)
tr
rise time
tf
fall time
Tcy(clk)
clock cycle time
Enable programming (pin EN)
−
10
40
ns
−
10
40
ns
100 −
−
ns
td(ENL-CLKH)
delay from enable active to rising clock edge
40
−
−
ns
td(CLKL-ENH)
delay from enable inactive to last falling clock edge
20
−
−
ns
tW(reg)(min)
minimum inactive pulse width when consecutively programming 150 −
−
ns
two different registers
tW(IFLO)(min)
minimum inactive pulse width when consecutively programming 150 −
−
ns
two IF divider ratios
tW(RFLO)(min) minimum inactive pulse width when consecutively programming 500 −
−
ns
two RF divider ratios
tsu(ENH-CLKH) enable set-up time to next rising clock edge
20
−
−
ns
Register serial input data (pin DATA)
tsu(DATA-CLK)
th(DATA-CLK)
set-up time DATA to CLK
hold time DATA to CLK
20
−
−
ns
20
−
−
ns
handbook, full pagewidth
t su (DATA-CLK)
CLK
t h (DATA-CLK)
DATA
MSB
EN
t d (ENL-CLKH)
Tcy (CLK)
ACTIVE
tf
tr
t d (CLKL-ENH)
tsu(ENH-CLKH)
LSB
ADDRESS
INACTIVE
FCA042
tW
2000 Feb 18
Fig.6 Serial bus timing diagram.
21