UPD30121F1-168-GA1 Ver la hoja de datos (PDF) - NEC => Renesas Technology
Número de pieza
componentes Descripción
Fabricante
UPD30121F1-168-GA1 Datasheet PDF : 76 Pages
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µPD30121
Signal
RSTOUT
MEMCS16#
IOCS16#
IOCHRDY
HLDRQ#
HLDACK#
SRAS#/GPIO4
SCAS#/GPIO5
SYSDIR/GPIO6
SPOWER/
GPIO7
(3/3)
I/O
Function
O This is the system bus reset signal. It is active when the VR4121 resets the system bus controller
(during bus timeout, manipulation of BCUCNTREG1 register, and power-down mode).
I This is a dynamic bus sizing request signal. Set this signal as active when system bus memory
accesses data in 16-bit width. This signal is invalid when 32-bit width is selected using LCD/high-speed
system bus.
I This is a dynamic bus sizing request signal. Set this signal as active when system bus I/O accesses
data in 16-bit width. This signal is invalid when 32-bit width is selected using LCD/high-speed system
bus.
I This is the system bus ready signal. Set this signal as active when the system bus controller is ready to
be accessed by the VR4121.
I This is a hold request signal for the system bus and DRAM bus that is sent from an external bus master.
O This is a hold acknowledge signal for the system bus and DRAM bus that is sent to an external bus
master.
I/O This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is a general-purpose I/O port.
<When accessing SDRAM>
This is the RAS signal for SDRAM and SROM only.
I/O This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is a general-purpose I/O port.
<When accessing SDRAM>
This is the CAS signal for SDRAM and SROM only.
I/O This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is a general-purpose I/O port.
<When accessing SDRAM>
This is the direction control signal for the buffer used to reduce the DATA bus's load.
I/O This function differs depending on the type of memory being accessed.
<When accessing DRAM (EDO type)>
This is a general-purpose I/O port.
<When accessing SDRAM>
This is the SDRAM's power supply control signal.
(2) Clock interface signals
Signal
RTCX1
RTCX2
CLKX1
CLKX2
FIRCLK
I/O
Function
I This is the 32.768-kHz oscillator’s input pin. It is connected to one side of a crystal resonator.
O This is the 32.768-kHz oscillator’s output pin. It is connected to one side of a crystal resonator.
I This is the 18.432-MHz oscillator’s input pin. It is connected to one side of a crystal resonator.
O This is the 18.432-MHz oscillator’s output pin. It is connected to one side of a crystal resonator.
I This is the 48-MHz clock input pin. Fix this at high level when FIR is not used.
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Data Sheet U14691EJ1V0DS00
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