N25Q128A13T12A0E Ver la hoja de datos (PDF) - Numonyx -> Micron

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N25Q128A13T12A0E

128-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface

Numonyx -> Micron 

N25Q128 - 3 V

XIP Operations

10.4

XIP Memory reset after a controller reset

If during the application life the system controller is reset during operation, and the device

features the RESET functionality (in devices with a dedicated part number), and the feature

has not been disabled, after the controller resets, the memory returns to POR state and

there is no issue. See Section 16: Ordering information.

In all the other cases, it is possible to exit the memory from the XIP mode by sending the

following rescue sequence at the first chip selection after a system reset:

DQ0= '1' for:

7 clock cycles within S low (S becomes high before 8th clock cycle)

+ 13 clock cycles within S low (S becomes high before 14th clock cycle)

+ 25 clock cycles within S low (S becomes high before 26th clock cycle)

The global effect is only to exit from XIP without any other reset.

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