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AN2577

Application note Using the eTPU angle clock

STMicroelectronics 

AN2577

eTPU angle clock hardware

Note:

hardware immediately suspends the count until an new tooth is detected. When the new

tooth is detected, the angle clock operation resumes from the count it held when the HOLD

bit was set.

Asserting HOLD stops the TCR2 count for exactly one tooth angle.

There are certain restrictions and limitations to the use of the various signals in the angle

clock TPR register.

● IPH may be used to reset the counter, if LAST is asserted when IPH is set.

● MISSCNT can be used to insert more than three missing teeth with the restriction that

if MISSCNT is to be written on the same tooth as the LAST bit is set, the two fields

must be written together.

● Do not use IPH to cancel a HOLD that is in progress. Simply clear the HOLD bit.

● When the tick counter is in high rate mode only IPH and HOLD can have immediate

effect. All other fields in the TPR are buffered until the angle clock exits High Rate

mode.

● If the TICKS field is changed before the angle clock goes into Halt mode, the tick

counter will attempt to use the new value immediately after the current tick occurs. Note

that the angle clock does not go into Halt mode until approximately one TRR time after

the last tick is counted.

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