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AN754

Understanding Microchip’s CAN Module Bit Timing

Microchip Technology 

Figure 5 shows how phase errors, other than zero,

cause the bit time to be lengthened or shortened.

Synchronization Rules:

1. Only recessive-to-dominant edges will be used

for synchronization.

2. Only one synchronization within one bit time is

allowed.

3. An edge will be used for synchronization only if

the value at the previous sample point differs

from the bus value immediately after the edge.

4. A transmitting node will not resynchronize on a

positive phase error (e > 0). This implies that a

transmitter will not resynchronize due to propa-

gation delays of it’s own transmitted message.

The receivers will synchronize normally.

5. If the absolute magnitude of the phase error is

greater than the SJW, then the appropriate

phase segment will be adjusted by an amount

equal to the SJW.

PUTTING IT ALL TOGETHER

As indicated previously, the CAN protocol implements

a non-destructive bitwise arbitration scheme that

allows multiple nodes to arbitrate for control of the bus.

Therefore, it is necessary for all the nodes to detect/

sample the bits within the same bit time. The relation-

ship between propagation delay and oscillator toler-

ance effect both the CAN data rate and the bus length.

Table 1 shows some commonly accepted bus lengths

versus data rates.

This application note does not cover all of the details for

configuring the bit time for all scenarios, however,

some general methodologies for configuring the CAN

bit time are covered.

TABLE 1:

CAN BIT RATE VS. BUS

LENGTH

Bit Rate (kb/s)

1000

500

250

125

62.5

Bus Length (m)

30

100

250

500

1000

Calculating Oscillator Tolerance for SJW

The bit stuffing rule guarantees that no more than five

like bits in a row will be transmitted during a message

frame. The only exception is at the end of the message

that includes ten recessive bits (one ACK delimiter,

seven end-of-frame bits, and three interframe space

bits).

AN754

Resynchronization can only occur on recessive-to-

dominant edges. This implies that there can be a max-

imum of ten bits between resynchronization due to bit

stuffing (Figure 6).

The oscillator tolerance between the slowest node and

the fastest node can be used to determine the mini-

mum SJW. Assuming Node A is the slow node (longest

bit time) and Node B is the fast node (shortest bit

time):

10tbit(A) > 10tbit(B) + tSJW(B)

Where:

tbit(n) = bit time of node “n”

tSJW(n) = SJW of node “n”

FIGURE 6:

MAXIMUM TIME BETWEEN

SYNCHRONIZATION EDGES

Synchronization

Edge

Bit

Time

EXAMPLE 1:

Find Minimum SJW

Given:

Nominal Bit Time = 1 µs

Oscillator tolerance = 1.25%

Note: #TQ per bit = 8

Find SJW minimum:

tbit(A) = 1.01200 µs

tbit(B) = 0.98875 µs

TQ(A) = 126.563 ns

TQ(B) = 123.438 ns

Using equation above:

tSJW(B) > 10tbit(A) - 10tbit(B) = 0.250 µs

#TQSJW > tSJW(B) / TQ(B) = 250 ns / 123.44 ns

= 2.025

#TQSJW = 3

 2001 Microchip Technology Inc.

DS00754A-page 7

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