H8/3060 Ver la hoja de datos (PDF) - Renesas Electronics

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H8/3060

Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Renesas Electronics 

Section 6 Bus Controller ................................................................................................... 125

6.1 Overview........................................................................................................................... 125

6.1.1 Features................................................................................................................ 125

6.1.2 Block Diagram..................................................................................................... 126

6.1.3 Pin Configuration ................................................................................................ 127

6.1.4 Register Configuration......................................................................................... 128

6.2 Register Descriptions........................................................................................................ 129

6.2.1 Bus Width Control Register (ABWCR)............................................................... 129

6.2.2 Access State Control Register (ASTCR) ............................................................. 130

6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 131

6.2.4 Bus Release Control Register (BRCR) ................................................................ 135

6.2.5 Bus Control Register (BCR) ................................................................................ 137

6.2.6 Chip Select Control Register (CSCR).................................................................. 139

6.2.7 Address Control Register (ADRCR) ................................................................... 140

6.3 Operation .......................................................................................................................... 141

6.3.1 Area Division....................................................................................................... 141

6.3.2 Bus Specifications ............................................................................................... 145

6.3.3 Memory Interfaces............................................................................................... 146

6.3.4 Chip Select Signals .............................................................................................. 147

6.3.5 Address Output Method....................................................................................... 148

6.4 Basic Bus Interface ........................................................................................................... 150

6.4.1 Overview.............................................................................................................. 150

6.4.2 Data Size and Data Alignment............................................................................. 150

6.4.3 Valid Strobes ....................................................................................................... 151

6.4.4 Memory Areas ..................................................................................................... 152

6.4.5 Basic Bus Control Signal Timing ........................................................................ 153

6.4.6 Wait Control ........................................................................................................ 160

6.5 Idle Cycle.......................................................................................................................... 162

6.5.1 Operation ............................................................................................................. 162

6.5.2 Pin States in Idle Cycle........................................................................................ 164

6.6 Bus Arbiter ....................................................................................................................... 165

6.6.1 Operation ............................................................................................................. 165

6.7 Register and Pin Input Timing.......................................................................................... 167

6.7.1 Register Write Timing ......................................................................................... 167

6.7.2 BREQ Pin Input Timing ...................................................................................... 168

Section 7 I/O Ports .............................................................................................................. 169

7.1 Overview........................................................................................................................... 169

7.2 Port 1................................................................................................................................. 173

7.2.1 Overview.............................................................................................................. 173

Rev. 6.00 Mar 18, 2005 page xiv of xlviii

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