F71882FG Ver la hoja de datos (PDF) - Feature Integration Technology Inc.

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Fabricante

F71882FG

Super Hardware Monitor + LPC I/O

Feature Integration Technology Inc. 

F71882

connect this pin to SPI BIOS chip select pin.

Function B: When using two SPI Flashes for primary

and back up BIOS, please connect this pin to primary

BIOS chip select pin.

FANCTL4

OD12-5v

AOUT

Fan 4 control output. This pin provides PWM

duty-cycle output or a voltage output.

61

GPIO12

I/OOD12t VSB General purpose IO.

SPI_MISO

INt 5 v

SPI master in/slave out pin.

FANCTL1_1

OD12-5v

Fan 1 control output. This pin provides PWM

duty-cycle open drain output for Intel 4-pin Fan.

62

GPIO13

I/OOD12t VSB General purpose IO.

SPI_MOSI

O12

SPI master out/slave in pin.

BEEP

OD24

Beep pin.

63

GPIO14

I/OOD12t VSB General purpose IO.

FWH_DIS

WDTRST#

SPI_CS1#

O12

OD12-5v

O12

Firmware hub disable

Watch dog timer signal output.

When using two SPI Flashes for primary and back up

BIOS, please connect this pin to back up BIOS chip

select pin.

67

OVT#

OD12-5v VSB Over temperature signal output.

6.7 ACPI Function Pins

Pin No.

64

65

74

75

76

77

Pin Name

GPIO15

LED_VSB

ALERT#

GPIO16

LED_VCC

Turbo2#

PCIRST1#

GPIO20

PCIRST2#

GPIO21

PCIRST3#

GPIO22

GPIO23

RSTCON#

78

ATXPG_IN

GPIO24

84

PWROK

Type

I/OOD12t

OD12

OD12

I/OOD12t

OD12

INts5v

OD12

I/OOD12

O12

I/OOD12

O12

I/OOD12

I/OOD12

OD12

AIN

I/OOD12t

OD12

PWR

VSB

VSB

VSB

VSB

VSB

VSB

VSB

VBAT

Description

General purpose IO.

Power LED for VSB.

Alert a signal when temperature over limit setting.

General purpose IO.

Power LED for VCC.

VID Turbo 2 enable control pin. (Patent Issue)

It is a output buffer of RSTCON# and LRESET#.

General purpose IO.

It is a output buffer of RSTCON# and LRESET#.

General purpose IO.

It is a output buffer of RSTCON# and LRESET#.

General purpose IO.

General purpose IO. (Default)

RESET Connect# with 50ms debouce function, it

connects to reset button, and also other reset source

on the motherboard.

ATX Power Good input.

General purpose IO.

PWROK function, It is power good signal of VCC,

which is delayed 400ms (default) as VCC arrives at

-11-

May, 2008

V0.28P

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