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MP4021A Ver la hoja de datos (PDF) - Monolithic Power Systems

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MP4021A Datasheet PDF : 21 Pages
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MP4021A—PRIMARY SIDE CONTROL OFFLINE LED CONTROLLER WITH ACTIVE PFC
Primary Inductor Current Detection
The system is based on the peak current mode
control. A sensing resistor is tied from the Source
of the MOSFET and ground to sample the
primary inductor peak current. Different from
working in CC mode, since the MP4021A
regulates the FB signal, the Real Current Control
signal from CS pin is shielded. The CS pin is just
applied as primary peak current detector like
traditional CV converter.
Tuning the value of the CS sensing resistor can
change the COMP level. With larger sensing
resistor, the COMP level is higher and with
smaller sensing resistor, the COMP level is lower.
So, select a suitable sensing resistor to avoid the
COMP level to trigger Upper/Lower COMP
Voltage.
In order to avoid hitting the current limit, the
voltage across the sensing resistor should be
less than 80% of the worst case current limit
voltage. And the clamp voltage on CS pin is
typical 2.5V.
Loop Compensation
Unlike voltage mode has only a single pole roll
off due to the output filter, the MP4021A uses
peak-current-mode control to achieve more
stable control loop.
Since MP4021A is designed with PFC feature, so
the loop response is very slow with large COMP
cap. For Primary-side CC mode, the part
samples the primary-side current. With large
output cap, although the output voltage builds up
slowly, the primary current should be not small,
so the COMP cap can not be charged to
overshoot. For CV mode control, the feedback
voltage is from the output voltage of the aux-
winding, which reflects the output voltage of the
secondary winding at flyback period. The impact
of the slow loop response results in that the
COMP level is easy to be charged to overshoot
or drops to normal level slowly.
Figure 13—COMP Pin Structure
A series capacitor-resistor combination net sets a
pole-zero combination to control the
characteristics of the control system.
The CCOMP1 is a big-value capacitor (2.2µF
to10µF) to achieve high PF and stable loop. The
RCOMP1 in series with CCOMP adds a zero in the
loop to improve the phase margin, it is helpful to
limit the start-up voltage spike. As an option, a
small-value capacitor CCOMP2 can also be applied
to add a high-frequency pole to achieve a
beneficial effect of attenuating high-frequency
noise.
Feedforward Compensation
In order to limit the output voltage spike and
improve the voltage regulation, adding feed-
forward compensation from aux-winding
feedback voltage to CS pin, shown in Figure 14,
Aux-winding
RVS1
FB
RVS2
ZD
RFF1
DVS RVLIM
CVS
AC Line
Pri-winding
GATE
CS
RFF2
RSENSE
Figure 14—The Feedforward Compensation
on CS Pin
MP4021A Rev.1.04
www.MonolithicPower.com
17
7/5/2013
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.

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