S3C70F4 Ver la hoja de datos (PDF) - Samsung

Número de pieza

componentes Descripción

Fabricante

S3C70F4

single-chip CMOS microcontroller

Samsung 

S3C70F2/C70F4/P70F4

ELECTRICAL DATA

Table 14-7. RAM Data Retention Supply Voltage in Stop Mode

(TA = – 40 °C to + 85 °C)

Parameter

Data retention supply voltage

Data retention supply current

Symbol

VDDDR

IDDDR

Conditions

–

VDDDR = 1.8 V

Min

Typ

Max

Unit

1.8

–

5.5

V

–

0.1

10

µA

Release signal set time

Oscillator stabilization wait

time (1)

tSREL

tWAIT

–

Released by RESET

Released by interrupt

0

–

–

µs

–

217 / fx

–

ms

–

(2)

–

ms

NOTES:

1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-

up.

2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.

TIMING WAVEFORMS

VDD

RESET

EXECUTION OF

STOP INSTRUCTION

STOP MODE

DATA RETENTION MODE

INTERNAL RESET

OPERATION

IDLE MODE

OPERATING

MODE

VDDDR

tSREL

tWAIT

Figure 14-2. Stop Mode Release Timing When Initiated by RESET

14-7

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