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ADF7023BCPZ Datasheet PDF : 112 Pages
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ADF7023
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
ADCIN_ATB3
RFIO_1P
RFIO_1N
RFO2
LNA
PA
RSSI/
LOGAMP
8-BIT
ADC
FSK
ASK
DEMOD
CDR
AFC
AGC
8-BIT RISC
PROCESSOR
4kB ROM
MAC
2kB RAM
256 BYTE
PACKET
RAM
PA DIVIDER
LOOP
FILTER
CHARGE
PUMP
PFD
26MHz OSC
64 BYTE
BBRAM
256 BYTE
MCR RAM
PA RAMP
PROFILE
ADF7023
DIVIDER
Σ-Δ
MODULATOR
fDEV
GAUSSIAN
FILTER
WAKE-UP CONTROL
TIMER UNIT
IRQ
CTRL
SPI
GPIO
TEST
DAC
CLOCK
DIVIDER
BIAS
ANALOG
TEST
TEMP
SENSOR
BATTERY
MONITOR
32kHz
OSC
32kHz
RCOSC
26MHz
OSC
IRQ_GP3
CS
MISO
SCLK
MOSI
GPIO1
CREGRFx CREGVCO CREGSYNTH CREGDIGx RBIAS
1GPIO REFERS TO PINS 17, 18, 19, 20, 25, AND 27.
XOSC32KN_ATB2 XOSC32KP_GP5_ATB1 XOSC26N XOSC26P
Figure 1.
GENERAL DESCRIPTION
The ADF7023 is a very low power, high performance, highly
integrated 2FSK/GFSK/OOK/MSK/GMSK transceiver designed
for operation in the 862 MHz to 928 MHz and 431 MHz to
464 MHz frequency bands, which cover the worldwide license-
free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It is suitable
for circuit applications that operate under the European ETSI
EN300-220, the North American FCC (Part 15), the Chinese short-
range wireless regulatory standards, or other similar regional
standards. Data rates from 1 kbps to 300 kbps are supported.
The transmit RF synthesizer contains a VCO and a low noise
fractional-N PLL with an output channel frequency resolution
of 400 Hz. The VCO operates at 2× or 4×, the fundamental
frequency to reduce spurious emissions. The receive and transmit
synthesizer bandwidths are automatically, and independently,
configured to achieve optimum phase noise, modulation quality,
and settling time. The transmitter output power is programmable
from −20 dBm to +13.5 dBm, with automatic PA ramping to
meet transient spurious specifications. The part possesses both
single-ended and differential PAs, which allows for Tx antenna
diversity.
The receiver is exceptionally linear, achieving an IP3 specification
of −12.2 dBm and −11.5 dBm at maximum gain and minimum
gain, respectively, and an IP2 specification of 18.5 dBm and
27 dBm at maximum gain and minimum gain, respectively. The
receiver achieves an interference blocking specification of 66 dB
at ±2 MHz offset and 74 dB at ±10 MHz offset. Thus, the part is
extremely resilient to the presence of interferers in spectrally
noisy environments. The receiver features a novel, high speed,
automatic frequency control (AFC) loop, allowing the PLL to
find and correct any RF frequency errors in the recovered packet.
A patent pending, image rejection calibration scheme is available
through a program download. The algorithm does not require
the use of an external RF source nor does it require any user
intervention once initiated. The results of the calibration can be
stored in nonvolatile memory for use on subsequent power-ups
of the transceiver.
The ADF7023 operates with a power supply range of 2.2 V to
3.6 V and has very low power consumption in both Tx and Rx
modes, enabling long lifetimes in battery-operated systems
while maintaining excellent RF performance. The device can
enter a low power sleep mode in which the configuration
settings are retained in BBRAM.
The ADF7023 features an ultralow power, on-chip,
communications processor. The communications processor,
which is an 8-bit RISC processor, performs the radio control,
packet management, and smart wake mode (SWM) functionality.
The communications processor eases the processing burden of
the companion processor by integrating the lower layers of a
typical communication protocol stack. The communications
processor also permits the download and execution of a set of
firmware modules that include image rejection (IR) calibration,
AES encryption, and Reed Solomon coding.
The communications processor provides a simple command-based
radio control interface for the host processor. A single-byte
command transitions the radio between states or performs a
radio function.
Rev. C | Page 4 of 112
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