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componentes Descripción

Fabricante

RTD2011

Flat Panel Display Controller

Realtek Semiconductor 

Realtek

RTD2011

4 Functional Description

4.1 Input

Digital Input (ITU 656)

RTD2011 is designed to connect the interface of digital signal from video decoder. Input data is latched

within a capture window defined in registers. The timing scheme designed for input devices are showed in

the following diagram.

There are not H sync V sync signals provided by the video decoder with ITU BT.656, these synchronal

signals have to be generated by decoding the EAV & SAV timing reference signals.

VGBCLK

VGB_R(Byte)

xxx

U0

Y0

V0

Y1

U2

Figure 5 Input YUV 4:2:2(8-bits) Timing

Only 254 of possible 256 8-bit words may be used to express a signal value, 0 and 255 are reserved for data

identification purposes. Video 8 data stream is as below:

Blanking

Timing reference 720 pixels YUV 422 DATA

period

code

… 80 10 FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2

Cbn: U(B-Y) colour difference component

Yn : luminance component

Crn: V(R-Y) colour difference component

Timing reference Blanking

code

period

… Cr718 Y719 FF 00 00 EAV 80 10 …

SAV/EAV format

Bit 7 Bit 6(F)

1

Field bit

1st field F=0

2nd field F=1

Bit 5(V)

Bit 4(H) Bit 3(P3) Bit 2(P2) Bit 1(P1) Bit 0(P0)

Vertical blanking bit V=1 H=0 in SAV Protection bits

Active video V=0

H=1 in EAV

Hardware can recognize the occurrence of EAV & SAV by detecting the 0xff , 0x00 , 0x00 data sequence,

and then generate the Hsync Vsync Field signals internally by decoding the fourth word of the timing

reference signal(EAV SAV). F & V change state synchronously with the EAV(End of active video)

reference code at the beginning of the digital line.

Bits P0, P1, P2, P3, have states dependent on the states of the bits F, V and H as shown below. At the

receiver this permits one-bit errors to be corrected and two-bits errors to be detected.

Confidential

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