BD6757KN Ver la hoja de datos (PDF) - ROHM Semiconductor

Número de pieza

componentes Descripción

Fabricante

BD6757KN

7ch System Lens Drivers for Digital Still Cameras / Single-lens Reflex Cameras

ROHM Semiconductor 

BD6757KN, BD6889GU

Technical Note

4) Ground pins and lines

Ensure a minimum GND pin potential in all operating conditions. Make sure that no pins are at a voltage below the GND

at any time, regardless of whether it is a transient signal or not.

When using both small signal GND and large current MGND patterns, it is recommended to isolate the two ground

patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and

voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to

change the GND wiring pattern of any external components, either.

The power supply and ground lines must be as short and thick as possible to reduce line impedance.

5) Thermal design

Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.

6) Pin short and wrong direction assembly of the device

Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any

connection error or if positive and ground power supply terminals are reversed. The IC may also be damaged if pins are

shorted together or are shorted to other circuit’s power lines.

7) Actions in strong magnetic field

Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction.

8) ASO

When using the IC, set the output transistor for the motor so that it does not exceed absolute maximum ratings or ASO.

9) Thermal shutdown circuit

If the junction temperature (Tjmax) reaches 175°C, the TSD circuit will operate, and the coil output circuit of the motor will

open. There is a temperature hysteresis of approximately 20°C (BD6757KN Typ.) and 25°C (BD6889GU Typ.). The TSD

circuit is designed only to shut off the IC in order to prevent runaway thermal operation. It is not designed to protect the IC

or guarantee its operation. The performance of the IC’s characteristics is not guaranteed and it is recommended that the

device is replaced after the TSD is activated.

10) Testing on application board

When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.

Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to, or

removing it from a jig or fixture, during the inspection process. Ground the IC during assembly steps as an antistatic

measure. Use similar precaution when transporting and storing the IC.

11) Application example

The application circuit is recommended for use. Make sure to confirm the adequacy of the characteristics. When using

the circuit with changes to the external circuit constants, make sure to leave an adequate margin for external components

including static and transitional characteristics as well as dispersion of the IC.

12) Regarding input pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated. P-N

junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or

transistor. For example, the relation between each potential is as follows:

When GND > Pin A, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic diode and transistor.

Parasitic elements can occur inevitably in the structure of the IC. The operation of parasitic elements can result in mutual

interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic elements

operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.

Pin A

Resistor

Pin A

Pin B

C

B

E

Transistor (NPN)

Pin B

N

N P+

Parasitic element

P

P+ N

P substrate

GND

Parasitic

element

N P+

Parasitic element

N

P

P+ N

P substrate

GND

GND

B

C

Other adjacent

elements

E

Parasitic

element

GND

Fig.21 Example of Simple IC Architecture

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© 2009 ROHM Co., Ltd. All rights reserved.

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2009.06 - Rev.A

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