RTL8111C Ver la hoja de datos (PDF) - Realtek Semiconductor

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RTL8111C

INTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS™ APPLICATIONS

Realtek Semiconductor 

RTL8111C

Datasheet

6.3. PHY Transceiver

6.3.1. PHY Transmitter

Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the RTL8111C

operates at 10/100/1000Mbps over standard CAT.5 UTP cable (100/1000Mbps), and CAT.3 UTP

cable (10Mbps).

GMII (1000Mbps) Mode

The RTL8111C’s PCS layer receives data bytes from the MAC through the GMII interface and performs

the generation of continuous code-groups through 4D-PAM5 coding technology. These code groups are

passed through a waveform-shaping filter to minimize EMI effect, and are transmitted onto the 4-pair

CAT5 cable at 125MBaud/s through a D/A converter.

MII (100Mbps) Mode

The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25MHz (TXC), are converted into

5B symbol code through 4B/5B coding technology, then through scrambling and serializing, are

converted to 125Mhz NRZ and NRZI signals. After that, the NRZI signals are passed to the MLT3

encoder, then to the D/A converter and transmitted onto the media.

MII (10Mbps) Mode

The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5MHz (TXC), are serialized into

10Mbps serial data. The 10Mbps serial data is converted into a Manchester-encoded data stream and is

transmitted onto the media by the D/A converter.

6.3.2. PHY Receiver

GMII (1000Mbps) Mode

Input signals from the media pass through the sophisticated on-chip hybrid circuit to separate the

transmitted signal from the input signal for effective reduction of near-end echo. Afterwards, the received

signal is processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)

correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5

decoding. Then, the 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of

125MHz. The Rx MAC retrieves the packet data from the receive MII/GMII interface and sends it to the

Rx Buffer Manager.

MII (100Mbps) Mode

The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing

recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII

interface in 4-bit-wide nibbles at a clock speed of 25MHz.

MII (10Mbps) Mode

The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is

processed with a Manchester decoder and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are

presented to the MII interface at a clock speed of 2.5MHz.

Integrated Gigabit Ethernet Controller for PCI Express

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Track ID: JATR-1076-21 Rev. 1.5

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