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VDP3104B

Video Processor Family

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VDP 31xxB

PRELIMINARY DATA SHEET

2.8.8. Chroma Transient Improvement

The intention of this block is to enhance the chroma

resolution. A correction signal is calculated by differenti-

ation of the color difference signals. The differentiation

can be selected according to the signal bandwidth, e.g.

for PAL/NTSC/SECAM or digital component signals,

respectively. The amplitude of the correction signal is

adjustable. Small noise amplitudes in the correction sig-

nal are suppressed by an adjustable coring circuit. To

eliminate ‘wrong colors’, which are caused by over and

undershoots at the chroma transition, the sharpened

chroma signals are limited to a proper value automati-

cally.

a)

Cr in

Cb in

t

b)

Ampl.

t

c)

Cr out

Cb out

t

a) Cr Cb input of DTI

b) Cr Cb input)Correction signal

c) sharpened and limited Cr Cb

Fig. 2–18: Digital Color Transient Improvement

2.8.9. Inverse Matrix

A 6-multiplier matrix transcodes the Cr and Cb signals

to R–Y, B–Y, and G–Y. The multipliers are also used to

adjust color saturation in the range of 0 to 2. The coeffi-

cients are signed and have a resolution of 9 bits. There

are separate matrix coefficients for main and side pic-

tures. The matrix computes:

R–Y+MR1*Cb)MR2*Cr

G–Y+MG1*Cb)MG2*Cr

B–Y+MB1*Cb)MB2*Cr

The initialization values for the matrix are computed

from the standard ITUR (CCIR) matrix:

ǒ Ǔ R

10

1.402 Y

G + 1 * 0.345 * 0.713 Cb

B

1 1.773 0

Cr

For a contrast setting of CTM+32, the matrix values are

scaled by a factor of 64, see also table 3–1.

2.8.10. RGB Processing

After adding the post-processed luma, the digital RGB

signals are limited to 10 bits. Three multipliers are used

to digitally adjust the white drive. Using the same multi-

pliers an average beam current limiter is implemented.

See also section 2.9.1. ‘CRT Measurement and Con-

trol’.

2.8.11. OSD Color Lookup Table

The VDP 31xxB has five input lines for an OSD signal.

This signal forms a 5-bit address for a color look-up table

(CLUT). The CLUT is a memory with 32 words where

each word holds a RGB value.

Bits 0 to 3 (bit 4+0) form the addresses for the ROM part

of the OSD, which generates full RGB signals (bit 0 to 2)

and half-contrast RGB signals (bit 3).

Bit 4 addresses the RAM part of the OSD with 16 freely

programmable colors, addressable with bit 0 to 3. The

programming is done via the I2C-bus.

The amplitude of the CLUT output signals can be ad-

justed separately for R, G and B via the I2C-bus. The

switchover between video RGB and OSD RGB is done

via the Priority bus.

18

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