MX25L8008E Ver la hoja de datos (PDF) - Macronix International

Número de pieza

componentes Descripción

Fabricante

MX25L8008E

8M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Macronix International 

MX25L8008E

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP

timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

page is protected by BP2-BP0 bits, the Page Program (PP) instruction will not be executed.

(12) Deep Power-down (DP)

The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby current

is reduced from standby to Deep Power-down). The Deep Power-down mode requires the Deep Power-down (DP)

instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruc-

tion are ignored.

The sequence is shown as Figure 22.

Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)

and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Power-

down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby

mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction

code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay

of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.

(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip

Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the

Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in

the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip

Select (CS#) must remain High for at least tRES2 (max), as specified in Table 9. Once in the Stand-by Power mode,

the device waits to be selected, so that it can receive, decode and execute instructions.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as "Table 6. ID

DEFINITIONS". This is not the same as RDID instruction. It is not recommended to use for new design. For new de-

sign, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be ex-

ecuted, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/

erase/write cycle in progress.

The sequence is shown in Figure 23 and Figure 24.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-

edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously

in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in

Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least

tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute

instruction.

The RDP instruction is for releasing from Deep Power Down Mode.

P/N: PM1944

REV. 1.1, DEC. 10, 2013

20

Share Link: