MBM29DL64DF-70
s FEATURES
• 0.17 µm Process Technology
• Two-bank Architecture for Simultaneous Read/Program and Read/Erase
• FlexBankTM *1
Bank A : 8 Mbit (8 KB × 8 and 64 KB × 15)
Bank B : 24 Mbit (64 KB × 48)
Bank C : 24 Mbit (64 KB × 48)
Bank D : 8 Mbit (8 KB × 8 and 64 KB × 15)
Two virtual Banks are chosen from the combination of four physical banks (Refer to “sFUNCTIONAL
DESCRIPTION FlexBankTM Architectureâ€and “Example of Virtual Banks Combinationâ€.)
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
• Single 3.0 V Read, Program, and Erase
Minimized system level power requirements
• Compatible with JEDEC-standard Commands
Uses the same software commands as E2PROMs
• Compatible with JEDEC-standard Worldwide Pinouts
48-pin TSOP (1) (Package suffix : TN − Normal Bend Type)
48-ball FBGA (Package suffix : PBT)
• Minimum 100,000 Program/Erase Cycles
• High Performance
70 ns maximum access time
• Sector Erase Architecture
Sixteen 4 Kword and one hundred twenty-six 32 Kword sectors in word mode
Sixteen 8 Kbyte and one hundred twenty-six 64 Kbyte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• HiddenROM Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable†command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC Input Pin
At VIL allows protection of “outermost†2 × 8 Kbytes on both ends of boot sectors, regardless of sector group
protection/unprotection status
At VACC, increases program performance
• Embedded EraseTM *2 Algorithms
Automatically preprograms and erases the chip or any sector
• Embedded ProgramTM *2 Algorithms
Automatically programs and verifies data at specified address
*1 : FlexBankTM is a trademark of Fujitsu Limited
*2 : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
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