NT5CB128M8DN/NT5CB64M16DP
NT5CC128M8DN/NT5CC64M16DP
1Gb DDR3 D-die SDRAM
Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance, additive
latency, WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on , , , high on
BA0 and low on BA1 and BA2, while controlling the states of address pins according to the following figure.
Fig. 9: MR1 Definition
REV 1.2
May. 2011
CONSUMER DRAM
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