TEA2164S Ver la hoja de datos (PDF) - STMicroelectronics

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Fabricante

TEA2164S

SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT

STMicroelectronics 

TEA2164S

IV - MAXIMUM DUTY CYCLE LIMITATION

Burst mode : The maximum duty cycle is controlled

by the voltage on Pin 9 (Figure 15).

Synchronized mode : Normally the maximum duty

cycle is set by the master circuit. However the

maximum conducting time will never exceed the

value given by the comparison of the oscillator

wave-form with the 2.5V internal threshold.

V - OUTPUT STAGE

TEA2164S output stage has been designed to

drive switching bipolar transistor.

- Each base drive begins with a positive pulse IBON

that realizes an efficient transistor turn-on.

Figure 15 : Maximum Duty Cycle Limitation

- After the starting pulse IBON, the base current is

proportional to the collector current. The current

gain is easily fixed by a resistor RB (Figure 16).

- A fast and safe transistor turn-off is realized by a

fast positive base current cut-off and by applying

a negative base drive which draws stored carri-

ers. Atypical 0.7s delay prevents from cross-con-

duction of positive and negative output stages.

Remark : In order to reduce power dissipation on

the positive output stage with the low gain transis-

tors, for high base currents the positive output

stage operates in saturated mode (Figure 17). This

can be achieved by using a resistor between VCC

and V+.

6 IO

9

e

Synchro ”ON”

V1

2.5V

S

OUTPUT

FLIP-FLOP

R

OSC

V1 = 4.5V - 1.25 x (e) ;

IO =

2.5V

RO

Figure 16 : Output Stage Architecture and Base Drive

16

15

IB

I BON

CURRENT

MIRROR

IC

IB

I Cmax

14

Virtual

Ground

V-

2

Pins

4-5-12-13

RS

RB

IC

t

t

IC

IB @ GF

V CM1

R S = ICmax

IC

RB

GF = =

IB 1000 x R S

12/16

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