M95256-DR, M95256, M95256-W, M95256-R
Instructions
The protection features of the device are summarized in Table 6.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W) input pin:
● If Write Protect (W) input pin is driven high, it is possible to write to the Status Register
(provided that the WEL bit has previously been set by a WREN instruction.
● If Write Protect (W) input pin is driven low, it is not possible to write to the Status
Register even if the WEL bit has previously been set by a WREN instruction. (Attempts
to write to the Status Register are rejected, and are not accepted for execution). As a
consequence, all the data bytes in the memory area that are software protected (SPM)
by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware
protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
● either by setting the SRWD bit after driving Write Protect (W) input pin low,
● or by driving Write Protect (W) input pin low after setting the SRWD bit.
Once entered in the Hardware Protected mode (HPM), the only way to exit the HPM mode is
to pull high the Write Protect (W) input pin.
If Write Protect (W) input pin is permanently tied high, the Hardware Protected mode (HPM)
can never be activated, and only the Software Protected mode (SPM), using the Block
Protect (BP1, BP0) bits of the Status Register, can be used.
Figure 9. Write Status Register (WRSR) sequence
S
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
C
Instruction
Status
Register In
D
76543210
High Impedance
MSB
Q
AI02282D
Doc ID 12276 Rev 11
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