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LT8580IDD

Boost/SEPIC/Inverting DC/DC Converter with 1A, 65V Switch, Soft-Start and Synchronization

Linear Technology 

LT8580

Applications Information

Layout Hints

As with all high frequency switchers, when considering

layout, care must be taken to achieve optimal electrical,

thermal and noise performance. One will not get adver-

tised performance with a careless layout. For maximum

efficiency, switch rise and fall times are typically in the

10nS to 20nS range. To prevent noise, both radiated and

conducted, the high speed switching current path, shown in

Figure 9, must be kept as short as possible. This is imple-

mented in the suggested layout of a boost configuration in

Figure 10. Shortening this path will also reduce the parasitic

trace inductance. At switch-off, this parasitic inductance

produces a flyback spike across the LT8580 switch. When

operating at higher currents and output voltages, with poor

layout, this spike can generate voltages across the LT8580

that may exceed its absolute maximum rating. A ground

plane should also be used under the switcher circuitry to

prevent interplane coupling and overall noise.

The VC and FBX components should be kept as far away

as practical from the switch node. The ground for these

components should be separated from the switch cur-

rent path. Failure to do so can result in poor stability or

subharmonic oscillation.

Board layout also has a significant effect on thermal re-

sistance. The exposed package ground pad is the copper

plate that runs under the LT8580 die. This is a good thermal

path for heat out of the package. Soldering the pad onto

L1

C1

D1

SW

LT8580

HIGH

VIN

FREQUENCY

SWITCHING

PATH

GND

VOUT

C2 LOAD

the board reduces die temperature and increases the power

capability of the LT8580. Provide as much copper area as

possible around this pad. Adding multiple feedthroughs

around the pad to the ground plane will also help. Figure 10

and Figure 11 show the recommended component place-

ment for the boost and SEPIC configurations, respectively.

Layout Hints for Inverting Topology

Figure 12 shows recommended component placement for

the dual inductor inverting topology. Input bypass capaci-

tor, C1, should be placed close to the LT8580, as shown.

The load should connect directly to the output capacitor,

C2, for best load regulation. The local ground may be tied

into the system ground plane at the C3 ground terminal.

The cut ground copper at D1’s cathode is essential to

obtain low noise. This important layout issue arises due

to the chopped nature of the currents flowing in Q1 and

D1. If they are both tied directly to the ground plane before

being combined, switching noise will be introduced into

the ground plane. It is almost impossible to get rid of this

noise, once present in the ground plane. The solution

is to tie D1’s cathode to the ground pin of the LT8580

before the combined currents are dumped in the ground

plane as drawn in Figure 2, Figure 13 and Figure 14. This

single layout technique can virtually eliminate high

frequency “spike” noise, so often present on switching

regulator outputs.

Differences from LT3580

LT8580 is very similar to LT3580. However, LT8580 does

deviate from LT3580 in a few areas:

• 65V, 1A switch

• 40V VIN and SHDN absolute maximum rating

• FB renamed to FBX

• 5V FBX absolute maximum rating

8580 F09

Figure 9. High Speed “Chopped” Switching

Path for Boost Topology

For more information www.linear.com/LT8580

8580f

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