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AT91M40800-33AU

AT91 ARM Thumb Microcontrollers

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7.5.2

To enter Tri-state mode, the pin NTRI must be held low during the last 10 clock cycles before the

rising edge of NRST. For normal operation the pin NTRI must be held high during reset by a

resistor of up to 400K Ohm.

NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.

Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1 is con-

nected to a device not including this pull-up, the user must make sure that a high level is tied on

NTRI while NRST is asserted.

JTAG/ICE Debug

ARM Standard Embedded In-circuit Emulation is supported via the JTAG/ICE port. The pins

TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host

computer via the external ICE interface.

In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the

microcontroller. This is not fully IEEE®1149.1 compliant.

7.6 Memory Controller

The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the

internal 32-bit address bus and defines three address spaces:

• Internal memories in the four lowest megabytes

• Middle space reserved for the external devices (memory or peripherals) controlled by the EBI

• Internal peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.

7.6.1

Internal Memories

The AT91M40800 microcontroller integrates 8K bytes of internal SRAM. All internal memories

are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word (32-bit)

accesses are supported and are executed within one cycle. Fetching Thumb or ARM instruc-

tions is supported and internal memory can store twice as many Thumb instructions as ARM

ones.

The SRAM is mapped at address 0x0 (after the remap command), allowing ARM7TDMI excep-

tion vectors between 0x0 and 0x20 to be modified by the software. The rest of the bank can be

used for stack allocation (to speed up context saving and restoring) or as data and program stor-

age for critical algorithms.

7.6.2

Boot Mode Select

The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI exe-

cutes the instruction stored at this address. This means that this address must be mapped in

nonvolatile memory after the reset.

The input level on the BMS pin during the last 10 clock cycles before the rising edge of the

NRST selects the type of boot memory (see Table 7-1).

8 AT91M40800

1348FS–ATARM–13-Apr-06

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