MC141516 Ver la hoja de datos (PDF) - Motorola => Freescale
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MC141516 Datasheet PDF : 16 Pages
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APPLICATION INFORMATION
SLEEP MODE
A sleep mode feature, the ZZ pin, has been implemented
on the MCM63P733A. It allows the system designer to place
the RAM in the lowest possible power condition by asserting
ZZ. The sleep mode timing diagram shows the different
modes of operation: Normal Operation, No READ/WRITE
Allowed, and Sleep Mode. Each mode has its own set of
constraints and conditions that are allowed.
Normal Operation: All inputs must meet setup and hold
times prior to sleep and tZZREC nanoseconds after re-
covering from sleep. Clock (K) must also meet cycle, high,
and low times during these periods. Two cycles prior to sleep,
initiation of either a read or write operation is not allowed.
No READ/WRITE: During the period of time just prior to
sleep and during recovery from sleep, the assertion of either
ADSC, ADSP, or any write signal is not allowed. If a write
operation occurs during these periods, the memory array
may be corrupted. Validity of data out from the RAM can not
be guaranteed immediately after ZZ is asserted (prior to
being in sleep).
Sleep Mode: The RAM automatically deselects itself. The
RAM disconnects its internal clock buffer. The external clock
may continue to run without impacting the RAMs sleep cur-
rent (IZZ). All inputs are allowed to toggle — the RAM will not
be selected and perform any reads or writes. However, if
inputs toggle, the IZZ (max) specification will not be met.
NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC
— and other high end MPU–based systems, these SRAMs
can be used in other high speed L2 cache or memory
applications that do not require the burst address feature.
Most L2 caches designed with a synchronous interface can
make use of the MCM63P733A. The burst counter feature of
the BurstRAM can be disabled, and the SRAM can be con-
figured to act upon a continuous stream of addresses. See
Figure 4.
CONTROL PIN TIE VALUES EXAMPLE (H ≥ VIH, L ≤ VIL)
Non–Burst ADSP ADSC ADV SE1 SE2 LBO
Sync Non–Burst, H
Pipelined SRAM
L
H
L
H
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
H
SE3
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 5. Example Configuration as Non–Burst Synchronous SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM 63P733A XX X X
Motorola Memory Prefix
Part Number
Blank = Trays, R = Tape and Reel
Speed (133 = 133 MHz, 117 = 117 MHz,
100 = 100 MHz, 90 = 90 MHz)
Package (TQ = TQFP)
Full Part Numbers — MCM63P733ATQ133 MCM63P733ATQ117 MCM63P733ATQ100 MCM63P733ATQ90
MCM63P733ATQ133R MCM63P733ATQ117R MCM63P733ATQ100R MCM63P733ATQ90R
MCM63P733A
14
MOTOROLA FAST SRAM
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