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MCP3422A3T-E/SN

18-Bit, Multi-Channel ΔΣ Analog-to-Digital Converter with I2C™ Interface and On-Board Reference

Microchip Technology 

MCP3422/3/4

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

MCP3422

MCP3423

MCP3424

DFN

MSOP,

SOIC

DFN

MSOP

SOIC,

TSSOP

1

1

1

1

1

2

2

2

2

2

7

7

4

4

3

8

8

5

5

4

6

6

3

3

5

3

3

6

6

6

4

4

7

7

7

5

5

8

8

8

—

—

9

9

9

—

—

10

10

10

—

—

—

—

11

—

—

—

—

12

—

—

—

—

13

—

—

—

—

14

9

—

11

—

—

Sym

CH1+

CH1-

CH2+

CH2-

VSS

VDD

SDA

SCL

Adr0

Adr1

CH3+

CH3-

CH4+

CH4-

EP

Description

Positive Differential Analog Input Pin of Channel 1

Negative Differential Analog Input Pin of Channel 1

Positive Differential Analog Input Pin of Channel 2

Negative Differential Analog Input Pin of Channel 2

Ground Pin

Positive Supply Voltage Pin

Bidirectional Serial Data Pin of the I2C Interface

Serial Clock Pin of the I2C Interface

I2C Address Selection Pin. See Section 5.3.2.

I2C Address Selection Pin. See Section 5.3.2.

Positive Differential Analog Input Pin of Channel 3

Negative Differential Analog Input Pin of Channel 3

Positive Differential Analog Input Pin of Channel 4

Negative Differential Analog Input Pin of Channel 4

Exposed Thermal Pad (EP); must be connected to

VSS.

3.1 Analog Inputs (CHn+, CHn-)

CHn+ and CHn- are differential input pins for

channel n. The user can also connect CHn- pin to VSS

for a single-ended operation. See Figure 6-4 for

differential and single-ended connection examples.

The maximum voltage range on each differential input

pin is from VSS-0.3V to VDD+0.3V. Any voltage below or

above this range will cause leakage currents through

the Electrostatic Discharge (ESD) diodes at the input

pins.

This ESD current can cause unexpected performance

of the device. The input voltage at the input pins should

be within the specified operating range defined in

Section 1.0 “Electrical Characteristics” and

Section 4.0 “Description of Device Operation”.

See Section 4.5 “Input Voltage Range” for more

details of the input voltage range.

Figure 3-1 shows the input structure of the device. The

device uses a switched capacitor input stage at the

front end. CPIN is the package pin capacitance and

typically about 4 pF. D1 and D2 are the ESD diodes.

CSAMPLE is the differential input sampling capacitor.

3.2 Supply Voltage (VDD, VSS)

VDD is the power supply pin for the device. This pin

requires an appropriate bypass ceramic capacitor of

about 0.1 µF to ground to attenuate high frequency

noise presented in application circuit board. An

additional 10 µF capacitor (tantalum) in parallel is also

recommended to further attenuate current spike

noises. The supply voltage (VDD) must be maintained

in the 2.7V to 5.5V range for specified operation.

VSS is the ground pin and the current return path of the

device. The user must connect the VSS pin to a ground

plane through a low impedance connection. If an

analog ground path is available in the application PCB

(printed circuit board), it is highly recommended that

the VSS pin be tied to the analog ground path or

isolated within an analog ground plane of the circuit

board.

© 2009 Microchip Technology Inc.

DS22088C-page 11

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