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M1A3P250-VQ100PP

ProASIC3 Flash Family FPGAs with Optional Soft ARM Support

Microsemi Corporation 

Revision

Revision 10

(continued)

July 2010

ProASIC3 Flash Family FPGAs

Changes

Page

"TBD" for 3.3 V LVCMOS Wide Range in Table 2-28 • I/O Output Buffer Maximum

Resistances1 through Table 2-30 • I/O Output Buffer Maximum Resistances1 was

replaced by "Same as regular 3.3 V" (SAR 33852).

2-25 to

2-27

The equations in the notes for Table 2-31 • I/O Weak Pull-Up/Pull-Down 2-27

Resistances were corrected (SAR 32470).

"TBD" for 3.3 V LVCMOS Wide Range in Table 2-32 • I/O Short Currents IOSH/IOSL

through Table 2-34 • I/O Short Currents IOSH/IOSL was replaced by "Same as

regular 3.3 V LVCMOS" (SAR 33852).

2-28 to

2-30

In the "3.3 V LVCMOS Wide Range" section, values were added to Table 2-47 2-38 to

through Table 2-49 for IOSL and IOSH, replacing "TBD" (SAR 33852).

2-39

The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 24916): 2-46

"It uses a 5 V–tolerant input buffer and push-pull output buffer."

The table notes were revised for Table 2-90 • LVDS Minimum and Maximum DC 2-65

Input and Output Levels (SAR 33859).

Values were added for FDDRIMAX and FDDOMAX in Table 2-102 • Input DDR 2-77, 2-79

Propagation Delays and Table 2-104 • Output DDR Propagation Delays (SAR

23919).

Table 2-115 • ProASIC3 CCC/PLL Specification was updated. A note was added to

indicate that when the CCC/PLL core is generated by Microsemi core generator

software, not all delay values of the specified delay increments are available (SAR

25705).

2-89

The following figures were deleted (SAR 29991). Reference was made to a new

application note, Simultaneous Read-Write Operations in Dual-Port SRAM for

Flash-Based cSoCs and FPGAs, which covers these cases in detail (SAR 21770).

Figure 2-34 • Write Access after Write onto Same Address

Figure 2-35 • Read Access after Write onto Same Address

Figure 2-35 • Read Access after Write onto Same Address

The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"

tables, Figure 2-38 • FIFO Reset, and the FIFO "Timing Characteristics" tables were

revised to ensure consistency with the software names (SARs 29991, 30510).

2-92,

2-94,

2-99,

2-101

The "Pin Descriptions" chapter has been added (SAR 21642).

3-1

Package names used in the "Package Pin Assignments" section were revised to 4-1

match standards given in Package Mechanical Drawings (SAR 27395).

The versioning system for datasheets has been changed. Datasheets are assigned N/A

a revision number that increments each time the datasheet is revised. The

"ProASIC3 Device Status" table on page III indicates the status for each device in

the device family.

Revision 14

5-3

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