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ACT8846

Advanced PMU for Multi-core Application Processors

Active-Semi, Inc 

ACT8846

Rev 4, 25-May-16

REGISTER AND BIT DESCRIPTIONS CONT’D

BLOCK ADDRESS BIT

NAME ACCESS

DESCRIPTION

PB

0xC0 [5:2]

-

R Reserved.

Watchdog Soft-Reset Enable. Set this bit to 1 to enable

PB

0xC0

1

WDSREN

R/W

watchdog function. When the watchdog timer expires, the PMU

commences a soft-reset routine. This bit is automatically reset to

0 when entering sleep mode.

Watchdog Power-Cycle Enable. Set this bit to 1 to enable

PB

0xC0

0

WDPCEN

R/W

watchdog function. When watchdog timer expires, the PMU

commence a power cycle. This bit is automatically reset to 0

when entering sleep mode.

PB

0xC1 [7:0] INTADR

Interrupt Address. It holds the address of the block that triggers

R the interrupt. This byte defaults to 0xFF and is automatically set

to 0xFF after being read. Bit 7 is the MSB while Bit 0 is the LSB.

PB

0xC2

7

PBASTAT

R

nPBIN Assertion Interrupt Status. The value of this bit is 1 if the

nPBIN Assertion Interrupt is triggered.

PB

0xC2

6 PBDSTAT

R

nPBIN De-assertion Interrupt Status. The value of this bit is 1 if

the nPBIN De-assertion Interrupt is triggered.

PB

0xC2

5

PBASTAT

nPBIN Status bit. This bit contains the real-time status of the

R nPBIN pin. The value of this bit is 1 if nPBIN is asserted, and is 0

if nPBIN is de-asserted.

PB

0xC2 [4:0]

-

R Reserved.

PB

0xC3 [7:5]

-

R Reserved.

PB

0xC3 [4] OFFSYS

R/W

Global Off Control. Set OFFSYSCLR[ ] to 1 first, then set this bit

to 1 to turn off all outputs.

PB

0xC3

[3] OFFSYSCLR

R/W

Global Off Control State Clear bit. Set bit to 1, then set OFFSYS

[ ] to 1 to turn off all outputs.

PB

0xC3 [2:1]

-

R Reserved.

PB

0xC3

0

SIPC

R/W

Software Initiated Power Cycle. When this bit is set, the PMU

commences a power cycle after 8ms delay.

PB

0xC5 [7:2]

-

R Reserved.

PB

0xC5

1

PCSTAT

R/W

Power-cycle Flag. The value of this bit is 1 after a power cycle.

This bit is automatically cleared to 0 after read.

PB

0xC5

0

SRSTAT

R/W

Soft-reset Flag. The value of this bit is 1 after a soft-reset. This

bit is automatically cleared to 0 after read.

Innovative PowerTM

ActivePMUTM is a trademark of Active-Semi.

I2CTM is a trademark of NXP.

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Copyright © 2016 Active-Semi, Inc.

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