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M1A3P250-QN144ES

1 – ProASIC®3 Flash Family FPGAs with Optional Soft ARM Support

Unspecified 

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a

D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections.

The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-

flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel

ProASIC family of third-generation architecture flash FPGAs. VersaTiles are connected with any of the four levels

of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile,

reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of

ProASIC3 devices via an IEEE 1532 JTAG interface.

VersaTiles

The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The

ProASIC3 VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-3 for VersaTile configurations.

LUT-3 Equivalent

X1

X2 LUT-3 Y

X3

D-Flip-Flop with Clear or Set

Data

Y

CLK

D-FF

CLR

Enable D-Flip-Flop with Clear or Set

Data

Y

CLK

D-FF

Enable

CLR

Figure 1-3 • VersaTile Configurations

User Nonvolatile FlashROM

Actel ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used

in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The core can be

individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely

load data over public networks (except in the A3P015 and A3P030 devices), as in security keys stored in the

FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back

either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can

only be programmed from the JTAG interface and cannot be programmed from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis

using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of

the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address

determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte.

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