M1A3P250-FGG144PP Ver la hoja de datos (PDF) - Unspecified

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M1A3P250-FGG144PP

1 – ProASIC®3 Flash Family FPGAs with Optional Soft ARM Support

Unspecified 

ProASIC3 DC and Switching Characteristics

Table 2-10 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings1

Applicable to Standard I/O Banks

Single-Ended

CLOAD (pF)

VCCI (V)

Static Power

PDC3 (mW)2

Dynamic Power

PAC10 (µW/MHz)3

3.3 V LVTTL /

35

3.3

3.3 V LVCMOS

–

431.08

2.5 V LVCMOS

35

2.5

–

247.36

1.8 V LVCMOS

35

1.8

–

128.46

1.5 V LVCMOS

35

1.5

(JESD8-11)

–

89.46

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength

and output slew.

2. PDC3 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

2-8

v1.1

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