SCAN18540TSSC Ver la hoja de datos (PDF) - Fairchild Semiconductor

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componentes Descripción

Fabricante

SCAN18540TSSC

Inverting Line Driver with 3-STATE Outputs

Fairchild Semiconductor 

Extended AC Electrical Characteristics

TA = 25°C

VCC = 5.0V

Symbol

Parameter

CL = 50 pF

18 Outputs

TA = −40°C to +85°C

VCC = 5.0V ± 0.5V

Units

Switching

CL = 250 pF

(Note 14)

(Note 15)

Min

Typ

Max

Min

Max

tPLH,

tPHL

tPZH,

tPZL

tPHZ,

tPLZ

tOSHL

(Note 18)

Propagation Delay

Data to Output

Output Enable Time

Output Disable Time

Pin to Pin Skew

HL Data to Output

3.0

11.0

3.0

11.0

2.5

11.5

2.5

14.0

2.0

11.5

2.0

11.5

0.5

1.0

4.0

13.0

ns

4.0

15.0

(Note 16)

ns

(Note 17)

ns

1.0

ns

tOSLH

Pin to Pin Skew

(Note 18) LH Data to Output

0.5

1.0

1.0

ns

Note 14: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-

HIGH, HIGH-to-LOW etc.).

Note 15: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load

capacitors in the standard AC load. This specification pertains to single output switching only.

Note 16: 3-STATE delays are load dominated and have been excluded from the datasheet.

Note 17: The Output Disable Time is dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.

Note 18: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.

The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination LOW-to-HIGH and/or HIGH-to-LOW.

Capacitance

Symbol

CIN

COUT

CPD

Parameter

Input Pin Capacitance

Output Pin Capacitance

Power Dissipation Capacitance

Typ

4.0

13.0

34.0

Units

pF

pF

pF

VCC = 5.0V

VCC = 5.0V

VCC = 5.0V

Conditions

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