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T8302

Internet Protocol Telephone Advanced RISC Machine (ARM®) Ethernet QoS Using IEEE® 802.1q

Agere -> LSI Corporation 

Data Sheet

July 2001

T8302 Internet Protocol Telephone

Advanced RISC Machine (ARM )

17 Key and Lamp Controller (KLC) (continued)

Table 202. Noscan Control Register

Bit #

Name

Bit #

31:8

7

31:8

RSVD

7

RESET

Name

RSVD

RESET

Address 0xE000 D100

6:2

1

RSVD

Noscan interval bit 1

Reserved.

Reset bit.

Description

0

Noscan interval bit 0

If 1, the KLC will reset. The KLC interrupt register and the KLC interrupt

enable register are left unchanged.

If 0, then the KLC will start (or continue) operation.

6:2

RSVD

Reserved.

1:0 NOSCAN INTERVAL Noscan interval. The noscan interval of the KLC can be changed through bits

0 and 1 of the KLC control register. These bits will be reset to 1 (for the

default interval) by a hardware reset.

Table 203. Noscan Delay Interval Encoding

Bit 1

0

0

1

1

Bit 0

0

1

0

1

Key Depression Noscan Interval

60 ms

22.5 ms

35 ms

47.5 ms (default)

Key Release Noscan Interval

50 ms

12.5 ms

25 ms

37.5 ms (default)

When a key is pressed, the KLC includes a debounce interval during which the beginning of an LED drive period is

executed before the key is located. After the key is located, the KLC must finish the suspended LED drive period.

This takes roughly 10 ms, that accounts for the difference in key depression and key release noscan intervals.

17.3.3 Key Scan Status Register

The KLC updates the key scan status register to indicate the current status of the key scan matrix. The KLC

samples the key matrix every 12.5 ms. When the KLC detects a key depression, it will wait for a 2.5 ms debounce

interval and then scan each row in its key matrix. When it locates the specific key depressed, it will place that key’s

row and column location into the key scan status register and set the key press bit to 1. The KLC will delay set-

ting the press bit to 1 until the following clock cycle to ensure that an asynchronous read from the microprocessor

will not read the press bit as 1 with an invalid code. After setting the key scan status register, the KLC will then

wait its programmed noscan interval, before acting on any changes during its sampling interval. After the noscan

interval has elapsed, the KLC will check that key once every 12.5 ms to determine if that key has been released.

When the KLC detects that the key is no longer depressed, it will reset the press bit to 0. The KLC will wait its pro-

grammed noscan interval again before it will act on any new key depressions found during its sampling interval.

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