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SERGBQA

SERCOS INTERFACE CONTROLLER

STMicroelectronics 

SERCON410B

PIN DESCRIPTION (Continued)

Table 1. SERCON410B I/O Port Function Summary (Continued)

Signal (s)

Pin (s)

IO

Function

SCLKO2

6

O

Clock output: outputs the SCLK clock divided by 2.

SCLKO4

5

O

Clock output: outputs the SCLK clock divided by 4.

MCLK

4

I

Master clock for telegram processing and timing control, frequency 12 to 20

MHz.

RSTN

10

I

Reset, active low. Must be zero for at least 50 ns after power on.

TEST

7

I

Test, active high. Has to be tied to VSS.

Puts outputs into high impedance state, active high: OUTZ is 1 puts all pins

OUTZ

11

I

into a high impedance state. The clocks are turned off and the circuit is

reset. For the in-circuit test and for turning on the powerdown mode.

NAND tree output. For the test at the semiconductor manufacturers and for

NDTRO

9

O

the connection test after board production. NDTRO is not set to a high

impedance state.

3,15,23,

33,42,

VSS

50,60,

70,81,

91

Ground pins.

1,8,19,

VDD

27,37,

55,65,

76,86

Power supply +5 V ± 5%.

8/30

®

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