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23LC512-I

512Kbit SPI Serial SRAM with SDI and SQI Interface

Microchip Technology 

23A512/23LC512

4.0 DUAL AND QUAD SERIAL

MODE

The 23A512/23LC512 also supports SDI (Serial Dual)

and SQI (Serial Quad) mode of operation when used

with compatible master devices. As a convention for

SDI mode of operation, two bits are entered per clock

using the SIO0 and SIO1 pins. Bits are clocked MSB

first.

For SQI mode of operation, four bits of data are entered

per clock, or one nibble per clock. The nibbles are

clocked MSB first.

4.1 Dual Interface Mode

The 23A512/23LC512 supports Serial Dual Input (SDI)

mode of operation. To enter SDI mode the EDIO com-

mand must be clocked in (Figure 4-1). It should be

noted that if the MCU resets before the SRAM, the user

will need to determine the serial mode of operation of

the SRAM and reset it accordingly. Byte read and write

sequence in SDI mode is shown in Figure 4-2 and

Figure 4-3.

FIGURE 4-1: ENTER SDI MODE (EDIO) FROM SPI MODE

CS

SCK

01234567

SI

0 01 1 1 0 11

High-Impedance

SO

4.2 Quad Interface Mode

In addition to the Serial Dual Interface (SDI) mode of

operation Serial Quad Interface (SQI) is also

supported. In this mode the HOLD functionality is not

available. To enter SQI mode the EQIO command must

be clocked in (Figure 4-4).

DS20005155B-page 14

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