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AD7173-8(Rev0) Ver la hoja de datos (PDF) - Analog Devices

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AD7173-8 Datasheet PDF : 64 Pages
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AD7173-8
Data Sheet
Parameter
Power Supply Rejection
(Line Regulation)
Load Regulation
Voltage Noise
Voltage Noise Density
Turn-On Settling Time
Long-Term Stability3
Short Circuit
EXTERNAL REFERENCE
Reference Input Voltage
Absolute Reference Input Voltage
Limits1
Buffers Disabled
Buffers Enabled
Average Reference Input Current
Buffers Disabled
Buffers Enabled
Average Reference Input Current Drift
External clock
Internal clock
Normal Mode Rejection1
Common-Mode Rejection
TEMPERATURE SENSOR
Accuracy
Sensitivity
BURNOUT CURRENTS
Source/Sink Current
BRIDGE POWER-DOWN SWITCH
RON
Allowable Currents
GENERAL-PURPOSE I/O (GPIO0, GPIO1,
GPO2, GPO3)
Input Mode Leakage Current1
Floating State Output Capacitance
AVDD1 − AVSS = 5 V
Output High Voltage, VOH1
Output Low Voltage, VOL1
Input High Voltage, VIH1
Input Low Voltage, VIL1
AVDD1 − AVSS = 3.3 V
Output High Voltage, VOH1
Output Low Voltage, VOL1
Input High Voltage, VIH1
Input Low Voltage, VIL1
CLOCK
Internal Clock
Frequency
Accuracy
Duty Cycle
Output Low Voltage, VOL
Output High Voltage, VOH
Crystal
Frequency
Start-Up Time
External Clock (CLKIO)
Duty Cycle1
Test Conditions/Comments
AVDD1 and AVDD2
∆VOUT/∆IL
eN, 0.1 Hz to 10 Hz
eN, 1 kHz
100 nF capacitor
1000 hours
ISC
Reference input = (REF+) − (REF−)
Buffers disabled
See the Rejection parameter
After user calibration at 25°C
Analog input buffers must be enabled
With respect to AVSS
ISOURCE = 200 µA
ISINK = 800 µA
ISOURCE = 200 µA
ISINK = 800 µA
Typical duty cycle 50:50 (maximum:minimum)
Rev. 0 | Page 4 of 64
Min
1
AVSS − 0.05
AVSS
−10
AVSS + 4
AVSS + 3
AVSS + 2.7
AVSS + 2
−2.5
0.8 × IOVDD
14
30:70
Typ
90
140
6.5
215
60
460
25
2.5
±9
±50
±5
±6
83
±2
477
±10
24
5
2
50:50
16
10
2
50:50
Max
AVDD1
Unit
dB
ppm/mA
µV rms
nV/√Hz
µs
ppm
mA
V
AVDD1 + 0.05 V
AVDD1
V
µA/V
nA
nA/V/°C
nA/V/°C
dB
°C
µV/°C
µA
Ω
16
mA
+10
µA
pF
V
AVSS + 0.4 V
V
AVSS + 0.7 V
V
AVSS + 0.27 V
V
AVSS + 0.45 V
MHz
+2.5
%
0.4
V
V
16.384
MHz
µs
2.048
MHz
70:30

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