E-STE10/100A Ver la hoja de datos (PDF) - STMicroelectronics

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E-STE10/100A

PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STMicroelectronics 

STE10/100A

Functional description

3.2

Network packet buffer management

3.2.1

Descriptor structure types

During normal network transmit operations, the STE10/100A transfers the data packets

from transmit buffers in the host’s memory to the STE10/100A’s transmit FIFO. For receive

operations, the STE10/100A transfers the data packet from its receive FIFO to receive

buffers in the host’s memory. The STE10/100A makes use of descriptors, data structures

which are built in host memory and contain pointers to the transmit and receive buffers and

maintain packet and frame parameters, status, and other information vital to controlling

network operation.

There are two types of structures employed to group descriptors, the Ring and the Chain,

both supported by the STE10/100A and shown below. The selection of structure type is

controlled by RCH (RDES1 bit 24) and TCH (TDES1 bit 24).

The transmit and receive buffers reside in the host’s memory. Any buffer can contain either a

complete or partial packet. A buffer may not contain more than one packet.

Ring structure

There are two buffers per descriptor in the ring structure. Support receive early interrupt.

Figure 5. Frame buffer ring structure

CSR3 or CSR4

Descriptor pointer

Descriptor

own

Length 2 Length 1

Buffer1 pointer

Buffer2 pointer

.

.

.

.

.

.

.

Data buffer

Data

Length 1

Data

Length 2

End of ring

PC00350

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