Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Pin Description
MAX5522
1
2
3
4
—
—
—
5
6
7
8
—
—
PIN
MAX5523 MAX5524
1
1
2
2
3
3
—
4
4
—
—
5, 11
—
6
5
7
6
8
7
9
8
10
—
12
—
EP
MAX5525
1
2
3
—
4
5, 11
6
7
8
9
10
12
EP
NAME
FUNCTION
CS
SCLK
Active-Low Digital Chip-Select Input
Serial-Interface Clock Input
DIN
REFIN
REFOUT
Serial-Interface Data Input
Reference Input
Reference Output
N.C.
No Connection. Leave N.C. inputs unconnected
(floating) or connected to GND.
FBB
OUTB
Channel B Feedback Input
Channel B Analog Voltage Output
VDD
GND
OUTA
Power Input. Connect VDD to a 1.8V to 5.5V power
supply. Bypass VDD to GND with a 0.1µF capacitor.
Ground
Channel A Analog Voltage Output
FBA
Channel A Feedback Input
Exposed Paddle Exposed Paddle. Connect EP to GND.
Functional Diagrams
SCLK
DIN
CS
POWER-
DOWN
CONTROL
CONTROL
LOGIC
AND
SHIFT
REGISTER
VDD
REFIN
MAX5522
INPUT
REGISTER
DAC
REGISTER
10-BIT DAC
INPUT
REGISTER
DAC
REGISTER
10-BIT DAC
OUTA
OUTB
GND
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