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MAX2117

Complete, Direct-Conversion Tuner for MMDS Applications

Maxim Integrated 

Complete, Direct-Conversion Tuner for

MMDS Applications

Figure 2 illustrates an example in which registers 0

through 2 are written with 0x0E, 0xD8, and 0xE1,

respectively.

Read Cycle

When addressed with a read command, the MAX2117

allows the master to read back a single register, or mul-

tiple successive registers.

A read cycle begins with the bus master issuing a

START condition followed by the 7 slave address bits

and a write bit (R/W = 0). The MAX2117 issues an ACK if

the slave address byte is successfully received. The bus

master must then send the address of the first register it

wishes to read (see Table 1 for register addresses). The

slave acknowledges the address. Then, a START condi-

tion is issued by the master, followed by the 7 slave

address bits and a read bit (R/W = 1). The MAX2117

issues an ACK if the slave address byte is successfully

received. The MAX2117 starts sending data MSB first

with each SCL clock cycle. At the 9th clock cycle, the

master can issue an ACK and continue to read succes-

sive registers, or the master can terminate the transmis-

sion by issuing a NACK. The read cycle does not

terminate until the master issues a STOP condition.

Figure 3 illustrates an example in which registers 0

through 2 are read back.

START

WRITE

DEVICE

ADDRESS

1100000

WRITE

WRITE DATA

WRITE DATA

WRITE DATA

R/W ACK REGISTER ACK TO REGISTER ACK TO REGISTER ACK TO REGISTER ACK

ADDRESS

0x00

0x01

0x02

STOP

0

—

0x00

—

0x0E

—

0xD8

—

0x0E1

—

Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively.

S

T

A

R

T

DEVICE

ADDRESS

1100000

R/W A

C

0K

REGISTER

ADDRESS

00000000

S

AT

CA

KR

T

DEVICE

ADDRESS

1100000

R/W A

C

1K

REG 00

DATA

xxxxxxxx

REG 01

A

DATA

C

K xxxxxxxx

REG 02

A DATA

C

K xxxxxxxx

NS

AT

CO

KP

Figure 3. Example: Receive data from read registers.

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