MAX14821 Ver la hoja de datos (PDF) - Maxim Integrated
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MAX14821 Datasheet PDF : 30 Pages
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MAX14821
IO-Link Device Transceiver
SPI Interface
The device communicates through an SPI-compatible
4-wire serial interface. The interface has three inputs—
clock (SCLK), chip select (CS), and data in (SDI)—and
one output, data out (SDO). The maximum SPI clock rate
for the device is 12MHz. The SPI interface complies with
clock polarity CPOL = 0 and clock phase CPHA = 0 (see
Figure 11 and Figure 12).
The SPI interface is not available when V5 or VL are not
present.
CS
SCLK
SDI
W
0
0
0
0
0
R1
R0
D7
D6
D5
D4
D3
D2
D1
D0
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE THAT INITIATES LATCHING OF SDI DATA
Figure 11. SPI Write Cycle
CS
SCLK
SDI X
R
0
0
0
0
0
R1 R0
X
SDO
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE THAT INITIATES LATCHING OF SDI DATA
= CLOCK EDGE THAT INITIATES WRITING OF SDO DATA
Figure 12. SPI Read Cycle
D7
D6
D5
D4
D3
D2
D1
D0
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