NT128D64SH4B1G Ver la hoja de datos (PDF) - Unspecified

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NT128D64SH4B1G

184 pin Unbuffered DDR DIMM

Unspecified 

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G

NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G

NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)

Unbuffered DDR DIMM

Operating, Standby, and Refresh Currents

TA = 0 °C ~ 70 °C; VDDQ= VDD= 2.5V ± 0.2V (PC2100/PC2700); VDDQ= VDD= 2.6V ± 0.1V (PC3200)

Symbol

Parameter/Condition

Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per

IDD0

clock cycle; address and control inputs changing once per clock cycle

Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and

IDD1

control inputs changing once per clock cycle

IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN)

IDD2N Idle Standby Current: CS ≥ VIH (MIN); all banks idle; CKE ≥ VIH (MIN); tCK = tCK (MIN); address and control inputs changing once

per clock cycle

IDD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE ≤ VIL (MAX); tCK = tCK (MIN)

Active Standby Current: one bank; active/precharge; CS ≥ VIH (MIN); CKE ≥ VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and

IDD3N

DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle

IDD4R

IDD4W

Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA

Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN)

IDD5 Auto-Refresh Current: tRC = tRFC (MIN)

IDD6 Self-Refresh Current: CKE ≤ 0.2V

Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of

IDD7

data changing at every transfer; tRC = tRC (min); IOUT = 0mA.

1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns.

3. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.

All IDD current values are calculated from device level.

Notes

1,2

1,2

1,2

1,2

1,2

1,2

1,2

1,2

1,2,3

1,2

1,2

REV 2.2

Aug 3, 2004

Preliminary

18

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NANYA reserves the right to change products and specifications without notice.

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