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IRS2573D

HID BALLAST CONTROL IC

International Rectifier 

IRS2573D

lamp has successfully ignited and the IC will enter General Mode. The IGN pin (ignition gate driver output) will

remain ‘high’ until the ignition timer has timed out.

Under-Voltage Fault Counter

The IC also includes an under-voltage fault counter at the VSENSE pin. Once the lamp has ignited, the lamp

voltage will decrease sharply to a very low voltage (20V typical). As the lamp warms up, the lamp voltage will

slowly increase until the nominal running voltage is reached (100V typical). If the lamp voltage remains too low

for too long, then this is a lamp fault condition and the ballast must shutdown. To detect this, the VSENSE pin

includes an under-voltage threshold of VOV(1/7.5). If the voltage at the VSENSE pin remains below VOV(1/7.5)

and the under-voltage fault counter times out (197sec typical), then the lamp is not warming up properly due to a

lamp fault condition (end of life, etc.) and the IC will enter fault mode and shutdown. If the voltage at the

VSENSE pin increases above VOV(1/7.5) before the under-voltage counter times out, then the lamp has

successfully warmed up and the IC will remain in general mode. A fast transient under-voltage detection is also

included at the VSENSE pin of the IC.

Fast Transient Under-Voltage Fault Counter

During normal running conditions, fast transient under-voltage spikes can occur on the lamp voltage due to

instabilities in the lamp arc. The resulting transients on the VSENSE pin will cycle below and above the

VOV(1/7.5) threshold quickly (<50us). If the number of events of these transients exceeds the maximum number

of events of the fault counter (16384 events typical), then the IC will enter fault mode and shutdown.

Good Counter

If no faults are detected for a long period of time (2730sec typical), as measured by the good counter, then the

fault counter and good counter will both be reset to zero. Also, each time a fault is counted, the good counter is

reset to zero.

Fault Reset

To exit Fault Mode and return to UVLO Mode, VCC can be decreased below UVLO- and back above UVLO+, or,

the RST pin can be increased above 2.5V.

PCB Layout Tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied to

the floating voltage pins (VB and VS) near the respective high voltage portions of the device.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high

voltage floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure

9). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops

must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT

collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to developing a

voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.

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