XWM8721EDS(2000) Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

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XWM8721EDS
(Rev.:2000)

Internet Audio DAC with Integrated Headphone Driver

Wolfson Microelectronics plc 

WM8721

DACLRC

BCLK

Product Preview

Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a LRCLK

transition, yet MSB is still transmitted first.

1/fs

LEFT CHANNEL

RIGHT CHANNEL

DACDAT

123

MSB

n-2 n-1 n

LSB

123

MSB

n-2 n-1 n

LSB

Figure 14 Right Justified Mode

DSP mode is where the left channel MSB is available on either the 1st or 2nd rising edge of BCLK

(selectable by LRP) following an LRCLK transition high. Right channel data immediately follows left

channel data.

1/fs

DACLRC

1 BCLK

BCLK

DACDAT

LEFT CHANNEL

RIGHT CHANNEL

123

n-2 n-1 n 1 2 3

MSB

LSB

Input Word Length (IWL)

n-2 n-1 n

Note: Input word length is defined by the IWL register, LRP = 1

Figure 15 DSP Mode

In all modes DACLRC must always change on the falling edge of BCLK, refer to Figure 12, Figure

13, Figure 14 and Figure 15.

Operating the digital audio interface in DSP mode allows ease of use for supporting the various

sample rates and word lengths. The only requirement is that all data is transferred within the correct

number of BCLK cycles to suit the chosen word length.

In order for the digital audio interface to offer similar support in the three other modes (Left Justified,

I2S and Right Justified), the DACLRC and BCLK frequencies, continuity and mark-space ratios need

more careful consideration.

In Slave mode, DACLRC inputs are not required to have a 50:50 mark-space ratio. BCLK input need

not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC

transition to clock the chosen data word length. The non-50:50 requirement on the LRC is of use in

some situations such as with a USB 12MHZ clock. Here simply dividing down a 12MHz clock within

the DSP to generate LRC and BCLK will not generate the appropriate DACLRC since it will no longer

change on the falling edge of BCLK. For example, with 12MHz/32k fs mode there are 375 MCLK per

LRC. In these situations DACLRC can be made non 50:50.

WOLFSON MICROELECTRONICS LTD

PP Rev 1.3 November 2000

17

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