TB62718AFG Ver la hoja de datos (PDF) - Marktech Optoelectronics
Número de pieza
componentes Descripción
Fabricante
TB62718AFG Datasheet PDF : 31 Pages
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TB62718AFG
Parallel data transfer PMW display data (data register PI REG2 [127:0])
Process PI DATA PI CLK PI LATCH PI SEL PO DATA
Operation and Function
1
L
H or L
(×16)
2
L
(×1)
Selects for input data of PWM display data (8 bit × 16).
L
H or L Data is transferred to PI REG2 on 16th positive edge of PI
CLK.
L
No
change
Holds the data transferred to PI REG2. Set is reflected on
PWM 256 grayscales from the next BLANK = L when it is
held.
Parallel data transfer timing (PWM data PI SEL = L, single device)
RESET
PI SEL
PI DATA
[7:0]
PI CLK
PWM data for OUT 15
PWM data for OUT 00
01H
02H
0EH 0FH
PI LATCH
PO DATA
[7:0]
00H 00H
Data held on positive edge of PI LATCH after data
transfer by single device (after 1 clock cycle)
01H
Indicates undefined logic state
after reset and before input.
PO DATA is synchronized with 16th clock
cycle after reset, and is output.
Parallel data transfer timing (PWM data PI SEL = L, two devices connected in cascade)
RESET
PI SEL
PI DATA
[7:0]
00H
01H
02H
PI CLK
0EH 0FH 10H 01H 02H
0EH 0FH 10H
PI LATCH
PO DATA [7:0]
(1st device)
PWM data for OUT 15
(1st device)
00H 00H
PWM data for OUT 00
(1st device)
01H 02H
0FH 10H 01H
Indicates undefined logic state
after reset and before input.
PO DATA is synchronized with 16th clock
cycle after reset, and the first data is output.
Data held on positive edge of PI
LATCH after data transfer by
two devices (32 clock cycles)
18
2005-04-20
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