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TB62718AFG

Controller and Driver for Full-color LED Modules and Panels

Marktech Optoelectronics 

TB62718AFG

Serial data transfer: dot adjustment DAC4. (data register SI REG2 [127:0])

Process SI DATA SI CLK SI LATCH SI SEL SO DATA

Operation and Function

1

L

H or L

(×128)

2

L

(×1)

L

H or L

Selects dot adjustment (128 bits) for input data. Data is

transferred to SI REG2 on 128th positive edge of SI CLK.

Holds the data transferred to SI REG2 on positive edge of

L

No SILATCH.

change Set is reflected on dot adjustment from the moment when

it is held.

Serial data transfer timing

(dot adjustment, SI SEL = L, single device)

RESET

SI SEL

There pairs of bits are Don’t care.

SI DATA

SI CLK

SI LATCH

Dot adjustment data for

OUT 15 (1st device).

Dot adjustment data for

OUT 00 (1st device).

Data held on positive edge of SI LATCH after data

transfer by single device (after 128 clock cycles)

SO DATA

(1st device)

Data reset by RESET = L

Indicates undefined logic state

after reset and before input.

SODATA is synchronized with 128th clock

cycle after reset, and the first data is output.

Serial data transfer timing

(dot adjustment, SI SEL = L, two devices connected in cascade)

RESET

SI SEL

There pairs of bits are Don’t care.

SI DATA

SI CLK

SI LATCH

Dot adjustment data for

OUT 15 (1st device).

Dot adjustment data for Dot adjustment data for

OUT 00 (1st device). OUT 15 (2nd device).

Dot adjustment data for

OUT 00 (2nd device).

SO DATA

(1st device)

Data reset by RESET = L

Indicates undefined logic state

after reset and before input.

SODATA is synchronized with 128th clock

cycle after reset, and the first data is output.

Data held on positive edge of SI LATCH after data

transfer by two devices (after 256 clock cycles)

14

2005-04-20

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