A29L400 Ver la hoja de datos (PDF) - AMIC Technology

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A29L400

512K X 8 Bit / 256K X 16 Bit C

AMIC Technology 

A29L400 Series

Note:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are write operation.

4. Data bits I/O15~I/O8 are don’t care for unlock and command cycles.

5. Address bits A17 - A11 are don't cares for unlock and command cycles, unless SA or PA required.

6. No unlock or command cycles required when reading array data.

7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high

(while the device is providing status data).

8. The fourth cycle of the autoselect command sequence is a read cycle.

9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more

information.

10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.

11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass

mode.

12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

13. The Erase Resume command is valid only during the Erase Suspend mode.

PRELIMINARY (October, 2002, Version 0.2)

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AMIC Technology, Inc.

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